2 * Copyright (C) 2012 - 2013 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/sama5d3_smc.h>
28 #include <asm/arch/at91_common.h>
29 #include <asm/arch/at91_pmc.h>
30 #include <asm/arch/at91_rstc.h>
31 #include <asm/arch/gpio.h>
32 #include <asm/arch/clk.h>
34 #include <atmel_lcdc.h>
35 #include <atmel_mci.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 /* ------------------------------------------------------------------------- */
43 * Miscelaneous platform dependent initialisations
46 #ifdef CONFIG_NAND_ATMEL
47 void sama5d3xek_nand_hw_init(void)
49 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
51 at91_periph_clk_enable(ATMEL_ID_SMC);
53 /* Configure SMC CS3 for NAND/SmartMedia */
54 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
55 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
57 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
58 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
60 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
62 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
63 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
64 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
65 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
66 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
67 AT91_SMC_MODE_EXNW_DISABLE |
68 #ifdef CONFIG_SYS_NAND_DBW_16
69 AT91_SMC_MODE_DBW_16 |
70 #else /* CONFIG_SYS_NAND_DBW_8 */
73 AT91_SMC_MODE_TDF_CYCLE(3),
79 static void sama5d3xek_usb_hw_init(void)
81 at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
82 at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
83 at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
87 #ifdef CONFIG_GENERIC_ATMEL_MCI
88 static void sama5d3xek_mci_hw_init(void)
92 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
97 vidinfo_t panel_info = {
101 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
105 .vl_left_margin = 64,
106 .vl_right_margin = 64,
108 .vl_upper_margin = 22,
109 .vl_lower_margin = 21,
110 .mmio = ATMEL_BASE_LCDC,
113 void lcd_enable(void)
117 void lcd_disable(void)
121 static void sama5d3xek_lcd_hw_init(void)
123 gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
125 /* The higher 8 bit of LCD is board related */
126 at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
127 at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
128 at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
129 at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
130 at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
131 at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
132 at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
133 at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
135 /* Configure lower 16 bit of LCD and enable clock */
139 #ifdef CONFIG_LCD_INFO
143 void lcd_show_board_info(void)
145 ulong dram_size, nand_size;
149 lcd_printf("%s\n", U_BOOT_VERSION);
150 lcd_printf("(C) 2013 ATMEL Corp\n");
151 lcd_printf("at91@atmel.com\n");
152 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
153 strmhz(temp, get_cpu_clk_rate()));
156 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
157 dram_size += gd->bd->bi_dram[i].size;
160 #ifdef CONFIG_NAND_ATMEL
161 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
162 nand_size += nand_info[i].size;
164 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
165 dram_size >> 20, nand_size >> 20);
167 #endif /* CONFIG_LCD_INFO */
168 #endif /* CONFIG_LCD */
170 int board_early_init_f(void)
172 at91_seriald_hw_init();
179 /* adress of boot parameters */
180 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
182 #ifdef CONFIG_NAND_ATMEL
183 sama5d3xek_nand_hw_init();
185 #ifdef CONFIG_CMD_USB
186 sama5d3xek_usb_hw_init();
188 #ifdef CONFIG_GENERIC_ATMEL_MCI
189 sama5d3xek_mci_hw_init();
191 #ifdef CONFIG_ATMEL_SPI
192 at91_spi0_hw_init(1 << 0);
200 sama5d3xek_lcd_hw_init();
207 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
208 CONFIG_SYS_SDRAM_SIZE);
212 int board_eth_init(bd_t *bis)
218 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
224 #ifdef CONFIG_GENERIC_ATMEL_MCI
225 int board_mmc_init(bd_t *bis)
229 rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
235 /* SPI chip select control */
236 #ifdef CONFIG_ATMEL_SPI
239 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
241 return bus == 0 && cs < 4;
244 void spi_cs_activate(struct spi_slave *slave)
248 at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
250 at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
252 at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
254 at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
260 void spi_cs_deactivate(struct spi_slave *slave)
264 at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
266 at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
268 at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
270 at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
275 #endif /* CONFIG_ATMEL_SPI */