2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2014, Bachmann electronic GmbH
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/imx-common/iomux-v3.h>
15 #include <asm/imx-common/sata.h>
16 #include <asm/imx-common/mxc_i2c.h>
17 #include <asm/imx-common/boot_mode.h>
18 #include <asm/arch/crm_regs.h>
20 #include <fsl_esdhc.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
31 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
32 OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
35 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
36 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
41 #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
44 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
45 PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
49 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
54 static iomux_v3_cfg_t const uart1_pads[] = {
55 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
59 static void setup_iomux_uart(void)
61 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
64 static iomux_v3_cfg_t const enet_pads[] = {
65 MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
76 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
79 MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
80 MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 static void setup_iomux_enet(void)
86 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
89 static iomux_v3_cfg_t const ecspi1_pads[] = {
90 MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
91 MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
92 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
93 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
94 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
97 static void setup_iomux_spi(void)
99 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
102 int board_spi_cs_gpio(unsigned bus, unsigned cs)
104 return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
107 static iomux_v3_cfg_t const feature_pads[] = {
109 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
112 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
115 static void setup_iomux_features(void)
117 imx_iomux_v3_setup_multiple_pads(feature_pads,
118 ARRAY_SIZE(feature_pads));
121 int board_early_init_f(void)
125 setup_iomux_features();
130 static iomux_v3_cfg_t const usdhc3_pads[] = {
131 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 iomux_v3_cfg_t const usdhc4_pads[] = {
145 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 int board_mmc_getcd(struct mmc *mmc)
155 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
158 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
159 gpio_direction_input(IMX_GPIO_NR(4, 5));
160 ret = gpio_get_value(IMX_GPIO_NR(4, 5));
162 gpio_direction_input(IMX_GPIO_NR(1, 5));
163 ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
169 struct fsl_esdhc_cfg usdhc_cfg[2] = {
174 int board_mmc_init(bd_t *bis)
179 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
180 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
182 usdhc_cfg[0].max_bus_width = 8;
183 usdhc_cfg[1].max_bus_width = 4;
185 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
188 imx_iomux_v3_setup_multiple_pads(
189 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
192 imx_iomux_v3_setup_multiple_pads(
193 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
196 printf("Warning: you configured more USDHC controllers"
197 "(%d) then supported by the board (%d)\n",
198 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
202 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
210 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
212 /* I2C3 - IO expander */
213 static struct i2c_pads_info i2c_pad_info2 = {
215 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
216 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
217 .gp = IMX_GPIO_NR(3, 17)
220 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
221 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
222 .gp = IMX_GPIO_NR(3, 18)
226 static iomux_v3_cfg_t const pwm_pad[] = {
227 MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
230 static void leds_on(void)
232 /* turn on all possible leds connected via GPIO expander */
234 pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
235 pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
238 static void backlight_lcd_off(void)
240 unsigned gpio = IMX_GPIO_NR(2, 0);
241 gpio_direction_output(gpio, 0);
243 gpio = IMX_GPIO_NR(2, 3);
244 gpio_direction_output(gpio, 0);
247 int board_eth_init(bd_t *bis)
249 uint32_t base = IMX_FEC_BASE;
250 struct mii_dev *bus = NULL;
251 struct phy_device *phydev = NULL;
256 bus = fec_get_miibus(base, -1);
260 /* scan phy 0 and 5 */
261 phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
267 /* depending on the phy address we can detect our board version */
268 if (phydev->addr == 0)
269 setenv("boardver", "");
271 setenv("boardver", "mr");
273 printf("using phy at %d\n", phydev->addr);
274 ret = fec_probe(bis, -1, base, bus, phydev);
276 printf("FEC MXC: %s:failed\n", __func__);
285 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
289 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
293 /* enable ecspi3 clocks */
294 enable_cspi_clock(1, 2);
296 #ifdef CONFIG_CMD_SATA
305 puts("Board: "CONFIG_SYS_BOARD"\n");
309 #ifdef CONFIG_CMD_BMODE
310 static const struct boot_mode board_boot_modes[] = {
311 /* 4 bit bus width */
312 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
317 int misc_init_r(void)
319 #ifdef CONFIG_CMD_BMODE
320 add_board_boot_modes(board_boot_modes);