4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/pxa.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 void balloon3_init_fpga(void);
22 * Miscelaneous platform dependent initialisations
27 /* We have RAM, disable cache */
31 /* arch number of vpac270 */
32 gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
34 /* adress of boot parameters */
35 gd->bd->bi_boot_params = 0xa0000100;
46 gd->ram_size = PHYS_SDRAM_1_SIZE;
50 void dram_init_banksize(void)
52 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
53 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
54 gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
56 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
57 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
58 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
62 int usb_board_init(void)
64 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
65 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
68 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
70 while (readl(UHCHR) & UHCHR_FSBIR)
73 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
74 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
76 /* Clear any OTG Pin Hold */
77 if (readl(PSSR) & PSSR_OTGPH)
78 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
80 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
81 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
83 /* Set port power control mask bits, only 3 ports. */
84 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
87 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
88 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
93 void usb_board_init_fail(void)
98 void usb_board_stop(void)
100 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
102 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
104 writel(readl(UHCCOMS) | 1, UHCCOMS);
107 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
113 #if defined(CONFIG_FPGA)
114 /* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
115 int fpga_pgm_fn(int nassert, int nflush, int cookie)
122 writel(0x100, GPCR3);
124 writel(0x100, GPSR3);
128 /* Check GPIO83 -- INITB */
129 int fpga_init_fn(int cookie)
131 return !(readl(GPLR2) & 0x80000);
134 /* Check GPIO84 -- BUSY */
135 int fpga_busy_fn(int cookie)
137 return !(readl(GPLR2) & 0x100000);
140 /* Check GPIO111 -- DONE */
141 int fpga_done_fn(int cookie)
143 return readl(GPLR3) & 0x8000;
146 /* Configure GPIO104 as GPIO and deassert it */
147 int fpga_pre_config_fn(int cookie)
149 writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
150 writel(0x100, GPCR3);
154 /* Configure GPIO104 as nSKTSEL */
155 int fpga_post_config_fn(int cookie)
157 writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
162 int fpga_wr_fn(int nassert_write, int flush, int cookie)
167 writel(0x100, GPCR3);
169 writel(0x100, GPSR3);
171 return nassert_write;
174 /* Write program to the FPGA */
175 int fpga_wdata_fn(uchar data, int flush, int cookie)
177 writeb(data, 0x10f00000);
181 /* Toggle Clock pin -- NO-OP */
182 int fpga_clk_fn(int assert_clk, int flush, int cookie)
187 /* Toggle ChipSelect pin -- NO-OP */
188 int fpga_cs_fn(int assert_clk, int flush, int cookie)
193 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
209 Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
210 (void *)&balloon3_fpga_fns, 0);
212 /* Initialize the FPGA */
213 void balloon3_init_fpga(void)
216 fpga_add(fpga_xilinx, &fpga);
219 void balloon3_init_fpga(void) {}
220 #endif /* CONFIG_FPGA */