2 * video.c - run splash screen on lcd
4 * Copyright (c) 2007-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
13 #include <asm/blackfin.h>
14 #include <asm/mach-common/bits/dma.h>
16 #include <linux/types.h>
19 int gunzip(void *, int, unsigned char *, unsigned long *);
23 #include <asm/mach-common/bits/eppi.h>
25 #include <asm/bfin_logo_230x230.h>
27 #define LCD_X_RES 480 /*Horizontal Resolution */
28 #define LCD_Y_RES 272 /* Vertical Resolution */
30 #define LCD_BPP 24 /* Bit Per Pixel */
31 #define LCD_PIXEL_SIZE (LCD_BPP / 8)
32 #define DMA_BUS_SIZE 32
33 #define ACTIVE_VIDEO_MEM_OFFSET 0
35 /* -- Horizontal synchronizing --
37 * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
38 * (LCY-W-06602A Page 9 of 22)
40 * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
42 * Period TH - 525 - Clock
43 * Pulse width THp - 41 - Clock
44 * Horizontal period THd - 480 - Clock
45 * Back porch THb - 2 - Clock
46 * Front porch THf - 2 - Clock
48 * -- Vertical synchronizing --
49 * Period TV - 286 - Line
50 * Pulse width TVp - 10 - Line
51 * Vertical period TVd - 272 - Line
52 * Back porch TVb - 2 - Line
53 * Front porch TVf - 2 - Line
56 #define LCD_CLK (8*1000*1000) /* 8MHz */
58 /* # active data to transfer after Horizontal Delay clock */
59 #define EPPI_HCOUNT LCD_X_RES
61 /* # active lines to transfer after Vertical Delay clock */
62 #define EPPI_VCOUNT LCD_Y_RES
64 /* Samples per Line = 480 (active data) + 45 (padding) */
67 /* Lines per Frame = 272 (active data) + 14 (padding) */
68 #define EPPI_FRAME 286
70 /* FS1 (Hsync) Width (Typical)*/
71 #define EPPI_FS1W_HBL 41
73 /* FS1 (Hsync) Period (Typical) */
74 #define EPPI_FS1P_AVPL EPPI_LINE
76 /* Horizontal Delay clock after assertion of Hsync (Typical) */
77 #define EPPI_HDELAY 43
79 /* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
80 #define EPPI_FS2W_LVB (EPPI_LINE * 10)
82 /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
83 #define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
85 /* Vertical Delay after assertion of Vsync (2 Lines) */
86 #define EPPI_VDELAY 12
88 #define EPPI_CLIP 0xFF00FF00
90 /* EPPI Control register configuration value for RGB out
92 * GP 2 frame sync mode,
93 * Internal Clock generation disabled, Internal FS generation enabled,
94 * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
95 * FS1 & FS2 are active high,
96 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
97 * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
99 * One (DMA) Channel Mode,
100 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
101 * Regular watermark - when FIFO is 100% full,
102 * Urgent watermark - when FIFO is 75% full
105 #define EPPI_CONTROL (0x20136E2E)
107 static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
109 u32 sclk = get_sclk();
111 /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
113 return (((sclk / target_ppi_clk) / 2) - 1);
118 u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
120 bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
121 bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
122 bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
123 bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
124 bfin_write_EPPI0_CLIP(EPPI_CLIP);
126 bfin_write_EPPI0_FRAME(EPPI_FRAME);
127 bfin_write_EPPI0_LINE(EPPI_LINE);
129 bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
130 bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
131 bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
132 bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
134 bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
137 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
138 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
140 #if defined(CONFIG_VIDEO_RGB666)
141 bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
144 bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
150 #define DEB2_URGENT 0x2000 /* DEB2 Urgent */
152 void Init_DMA(void *dst)
155 #if defined(CONFIG_DEB_DMA_URGENT)
156 *pEBIU_DDRQUE |= DEB2_URGENT;
159 *pDMA12_START_ADDR = dst;
162 *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE;
163 *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8;
166 *pDMA12_Y_COUNT = LCD_Y_RES;
167 *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8;
171 WDSIZE_32 | /* 32 bit DMA */
173 FLOW_AUTO; /* autobuffer mode */
176 void Init_Ports(void)
178 *pPORTF_MUX = 0x00000000;
179 *pPORTF_FER |= 0xFFFF; /* PPI0..15 */
181 *pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
182 *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */
184 #if !defined(CONFIG_VIDEO_RGB666)
185 *pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
186 *pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
187 *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */
190 *pPORTE_FER &= ~PE3; /* DISP */
191 *pPORTE_DIR_SET = PE3;
198 *pDMA12_CONFIG |= DMAEN;
201 void DisableDMA(void)
203 *pDMA12_CONFIG &= ~DMAEN;
206 /* enable and disable PPI functions */
209 bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
212 void DisablePPI(void)
214 bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
217 int video_init(void *dst)
228 static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
231 blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
233 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
235 /* Setup destination start address */
236 bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
237 + (y * LCD_X_RES * LCD_PIXEL_SIZE));
238 /* Setup destination xcount */
239 bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
240 /* Setup destination xmodify */
241 bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
243 /* Setup destination ycount */
244 bfin_write_MDMA_D0_Y_COUNT(logo->height);
245 /* Setup destination ymodify */
246 bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
249 /* Setup Source start address */
250 bfin_write_MDMA_S0_START_ADDR(logo->data);
251 /* Setup Source xcount */
252 bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
253 /* Setup Source xmodify */
254 bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
256 /* Setup Source ycount */
257 bfin_write_MDMA_S0_Y_COUNT(logo->height);
258 /* Setup Source ymodify */
259 bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
262 /* Enable source DMA */
263 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
265 bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
267 while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
269 bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
270 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
274 void video_putc(const char c)
278 void video_puts(const char *s)
282 int drv_video_init(void)
284 int error, devices = 1;
288 u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
290 dst = malloc(fbmem_size);
293 printf("Failed to alloc FB memory\n");
297 #ifdef EASYLOGO_ENABLE_GZIP
298 unsigned char *data = EASYLOGO_DECOMP_BUFFER;
299 unsigned long src_len = EASYLOGO_ENABLE_GZIP;
300 if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
301 puts("Failed to decompress logo\n");
305 bfin_logo.data = data;
308 memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
310 dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
311 (LCD_X_RES - bfin_logo.width) / 2,
312 (LCD_Y_RES - bfin_logo.height) / 2);
314 video_init(dst); /* Video initialization */
316 memset(&videodev, 0, sizeof(videodev));
318 strcpy(videodev.name, "video");
319 videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
320 videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
321 videodev.putc = video_putc; /* 'putc' function */
322 videodev.puts = video_puts; /* 'puts' function */
324 error = device_register(&videodev);
326 return (error == 0) ? devices : error;