2 * SPL data and initialization for CompuLab CL-SOM-AM57x board
4 * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
6 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/omap_common.h>
13 #include <asm/arch/sys_proto.h>
15 static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
16 .dmm_lisa_map_3 = 0x80740300,
20 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
22 /* Disable SDRAM controller EMIF2 for single core SOC */
23 *dmm_lisa_regs = &cl_som_am57x_lisa_regs;
24 if (omap_revision() == DRA722_ES1_0) {
25 ((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 =
30 static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
31 .sdram_config_init = 0x61852332,
32 .sdram_config = 0x61852332,
33 .sdram_config2 = 0x00000000,
34 .ref_ctrl = 0x000040f1,
35 .ref_ctrl_final = 0x00001040,
36 .sdram_tim1 = 0xeeef36f3,
37 .sdram_tim2 = 0x348f7fda,
38 .sdram_tim3 = 0x027f88a8,
39 .read_idle_ctrl = 0x00050000,
40 .zq_config = 0x1007190b,
41 .temp_alert_config = 0x00000000,
42 .emif_ddr_phy_ctlr_1_init = 0x0034400b,
43 .emif_ddr_phy_ctlr_1 = 0x0e34400b,
44 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
45 .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
46 .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
47 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
48 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
49 .emif_rd_wr_lvl_rmp_win = 0x00000000,
50 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
51 .emif_rd_wr_lvl_ctl = 0x00000000,
52 .emif_rd_wr_exec_thresh = 0x00000305
55 /* Ext phy ctrl regs 1-35 */
56 static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
98 static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
99 .sdram_config_init = 0x61852332,
100 .sdram_config = 0x61852332,
101 .sdram_config2 = 0x00000000,
102 .ref_ctrl = 0x000040f1,
103 .ref_ctrl_final = 0x00001040,
104 .sdram_tim1 = 0xeeef36f3,
105 .sdram_tim2 = 0x348f7fda,
106 .sdram_tim3 = 0x027f88a8,
107 .read_idle_ctrl = 0x00050000,
108 .zq_config = 0x1007190b,
109 .temp_alert_config = 0x00000000,
110 .emif_ddr_phy_ctlr_1_init = 0x0034400b,
111 .emif_ddr_phy_ctlr_1 = 0x0e34400b,
112 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
113 .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
114 .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
115 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
116 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
117 .emif_rd_wr_lvl_rmp_win = 0x00000000,
118 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
119 .emif_rd_wr_lvl_ctl = 0x00000000,
120 .emif_rd_wr_exec_thresh = 0x00000305
123 static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
163 static struct vcores_data cl_som_am57x_volts = {
164 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
165 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
166 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
167 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
168 .mpu.pmic = &tps659038,
170 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
171 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
172 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
173 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
174 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
175 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
176 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
177 .eve.addr = TPS659038_REG_ADDR_SMPS45,
178 .eve.pmic = &tps659038,
180 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
181 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
182 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
183 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
184 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
185 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
186 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
187 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
188 .gpu.pmic = &tps659038,
190 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
191 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
192 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
193 .core.addr = TPS659038_REG_ADDR_SMPS7,
194 .core.pmic = &tps659038,
196 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
197 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
198 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
199 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
200 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
201 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
202 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
203 .iva.addr = TPS659038_REG_ADDR_SMPS8,
204 .iva.pmic = &tps659038,
207 void hw_data_init(void)
209 *prcm = &dra7xx_prcm;
210 *dplls_data = &dra7xx_dplls;
211 *omap_vcores = &cl_som_am57x_volts;
212 *ctrl = &dra7xx_ctrl;
215 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
219 *regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
222 *regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
227 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
231 *regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
232 *size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
235 *regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
236 *size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);