2 * Board functions for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <fsl_esdhc.h>
16 #include <fdt_support.h>
19 #include <asm/arch/crm_regs.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/iomux.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/imx-common/mxc_i2c.h>
24 #include <asm/imx-common/sata.h>
25 #include <asm/imx-common/video.h>
28 #include <dm/platform_data/serial_mxc.h>
30 #include "../common/eeprom.h"
31 #include "../common/common.h"
33 DECLARE_GLOBAL_DATA_PTR;
35 #ifdef CONFIG_SPLASH_SCREEN
36 static struct splash_location cm_fx6_splash_locations[] = {
39 .storage = SPLASH_STORAGE_SF,
44 int splash_screen_prepare(void)
46 return splash_source_load(cm_fx6_splash_locations,
47 ARRAY_SIZE(cm_fx6_splash_locations));
51 #ifdef CONFIG_IMX_HDMI
52 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
54 imx_enable_hdmi_phy();
57 struct display_info_t const displays[] = {
61 .pixfmt = IPU_PIX_FMT_RGB24,
62 .detect = detect_hdmi,
63 .enable = cm_fx6_enable_hdmi,
77 .vmode = FB_VMODE_NONINTERLACED,
81 size_t display_count = ARRAY_SIZE(displays);
83 static void cm_fx6_setup_display(void)
85 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
86 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
91 reg = __raw_readl(&mxc_ccm->CCGR3);
92 reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
93 writel(reg, &mxc_ccm->CCGR3);
94 clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
97 static inline void cm_fx6_setup_display(void) {}
98 #endif /* CONFIG_VIDEO_IPUV3 */
100 #ifdef CONFIG_DWC_AHSATA
101 static int cm_fx6_issd_gpios[] = {
102 /* The order of the GPIOs in the array is important! */
107 CM_FX6_SATA_NSTANDBY1,
108 CM_FX6_SATA_NSTANDBY2,
111 static void cm_fx6_sata_power(int on)
115 if (!on) { /* tell the iSSD that the power will be removed */
116 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
120 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
121 gpio_direction_output(cm_fx6_issd_gpios[i], on);
125 if (!on) /* for compatibility lower the power loss interrupt */
126 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
129 static iomux_v3_cfg_t const sata_pads[] = {
131 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
132 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
133 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
134 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
136 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
137 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
138 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
139 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
140 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
143 static int cm_fx6_setup_issd(void)
147 SETUP_IOMUX_PADS(sata_pads);
149 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
150 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
155 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
162 #define CM_FX6_SATA_INIT_RETRIES 10
163 int sata_initialize(void)
167 /* Make sure this gpio has logical 0 value */
168 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
170 cm_fx6_sata_power(1);
172 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
175 printf("SATA setup failed: %d\n", err);
181 err = __sata_initialize();
185 /* There is no device on the SATA port */
186 if (sata_port_status(0, 0) == 0)
189 /* There's a device, but link not established. Retry */
198 cm_fx6_sata_power(0);
204 static int cm_fx6_setup_issd(void) { return 0; }
207 #ifdef CONFIG_SYS_I2C_MXC
208 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
209 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
210 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
213 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
214 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
216 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
217 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
221 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
222 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
224 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
225 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
229 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
230 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
232 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
233 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
237 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
241 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
243 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
248 static int cm_fx6_setup_i2c(void)
252 /* i2c<x>_pads are wierd macro variables; we can't use an array */
253 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
256 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
259 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
266 static int cm_fx6_setup_i2c(void) { return 0; }
269 #ifdef CONFIG_USB_EHCI_MX6
270 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
271 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
272 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
273 #define MX6_USBNC_BASEADDR 0x2184800
274 #define USBNC_USB_H1_PWR_POL (1 << 9)
276 static int cm_fx6_setup_usb_host(void)
280 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
284 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
285 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
290 static int cm_fx6_setup_usb_otg(void)
293 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
295 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
297 printf("USB OTG pwr gpio request failed: %d\n", err);
301 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
302 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
303 MUX_PAD_CTRL(WEAK_PULLDOWN));
304 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
305 /* disable ext. charger detect, or it'll affect signal quality at dp. */
306 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
309 int board_ehci_hcd_init(int port)
312 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
314 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
318 /* Set PWR polarity to match power switch's enable polarity */
319 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
320 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
325 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
334 int board_ehci_power(int port, int on)
337 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
342 static int cm_fx6_setup_usb_otg(void) { return 0; }
343 static int cm_fx6_setup_usb_host(void) { return 0; }
346 #ifdef CONFIG_FEC_MXC
347 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
348 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
350 static int mx6_rgmii_rework(struct phy_device *phydev)
354 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
355 * which cause ethernet link down/up issue, so disable SmartEEE
357 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
358 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
359 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
360 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
362 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
364 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
365 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
366 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
367 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
369 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
372 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
374 /* introduce tx clock delay */
375 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
376 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
378 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
383 int board_phy_config(struct phy_device *phydev)
385 mx6_rgmii_rework(phydev);
387 if (phydev->drv->config)
388 return phydev->drv->config(phydev);
393 static iomux_v3_cfg_t const enet_pads[] = {
394 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
395 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
396 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
397 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
398 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
399 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
400 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
401 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
402 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
403 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
404 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
405 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
406 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
407 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
408 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
409 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
410 MUX_PAD_CTRL(ENET_PAD_CTRL)),
411 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
412 MUX_PAD_CTRL(ENET_PAD_CTRL)),
413 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
414 MUX_PAD_CTRL(ENET_PAD_CTRL)),
417 static int handle_mac_address(char *env_var, uint eeprom_bus)
419 unsigned char enetaddr[6];
422 rc = eth_getenv_enetaddr(env_var, enetaddr);
426 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
430 if (!is_valid_ethaddr(enetaddr))
433 return eth_setenv_enetaddr(env_var, enetaddr);
436 #define SB_FX6_I2C_EEPROM_BUS 0
437 #define NO_MAC_ADDR "No MAC address found for %s\n"
438 int board_eth_init(bd_t *bis)
442 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
443 printf(NO_MAC_ADDR, "primary NIC");
445 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
446 printf(NO_MAC_ADDR, "secondary NIC");
448 SETUP_IOMUX_PADS(enet_pads);
450 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
452 printf("Etnernet NRST gpio request failed: %d\n", err);
453 gpio_direction_output(CM_FX6_ENET_NRST, 0);
455 gpio_set_value(CM_FX6_ENET_NRST, 1);
457 return cpu_eth_init(bis);
461 #ifdef CONFIG_NAND_MXS
462 static iomux_v3_cfg_t const nand_pads[] = {
463 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
464 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
465 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
466 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
467 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
468 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
469 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
470 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
471 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
472 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
473 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
474 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
475 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
476 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
479 static void cm_fx6_setup_gpmi_nand(void)
481 SETUP_IOMUX_PADS(nand_pads);
482 /* Enable clock roots */
483 enable_usdhc_clk(1, 3);
484 enable_usdhc_clk(1, 4);
486 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
487 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
488 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
491 static void cm_fx6_setup_gpmi_nand(void) {}
494 #ifdef CONFIG_FSL_ESDHC
495 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
501 static enum mxc_clock usdhc_clk[3] = {
507 int board_mmc_init(bd_t *bis)
511 cm_fx6_set_usdhc_iomux();
512 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
513 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
514 usdhc_cfg[i].max_bus_width = 4;
515 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
516 enable_usdhc_clk(1, i);
523 #ifdef CONFIG_MXC_SPI
524 int cm_fx6_setup_ecspi(void)
526 cm_fx6_set_ecspi_iomux();
527 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
530 int cm_fx6_setup_ecspi(void) { return 0; }
533 #ifdef CONFIG_OF_BOARD_SETUP
534 int ft_board_setup(void *blob, bd_t *bd)
539 if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
540 fdt_find_and_setprop(blob,
541 "/soc/aips-bus@02100000/ethernet@02188000",
542 "local-mac-address", enetaddr, 6, 1);
545 if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
546 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
558 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
559 cm_fx6_setup_gpmi_nand();
561 ret = cm_fx6_setup_ecspi();
563 printf("Warning: ECSPI setup failed: %d\n", ret);
565 ret = cm_fx6_setup_usb_otg();
567 printf("Warning: USB OTG setup failed: %d\n", ret);
569 ret = cm_fx6_setup_usb_host();
571 printf("Warning: USB host setup failed: %d\n", ret);
574 * cm-fx6 may have iSSD not assembled and in this case it has
575 * bypasses for a (m)SATA socket on the baseboard. The socketed
576 * device is not controlled by those GPIOs. So just print a warning
577 * if the setup fails.
579 ret = cm_fx6_setup_issd();
581 printf("Warning: iSSD setup failed: %d\n", ret);
583 /* Warn on failure but do not abort boot */
584 ret = cm_fx6_setup_i2c();
586 printf("Warning: I2C setup failed: %d\n", ret);
588 cm_fx6_setup_display();
595 puts("Board: CM-FX6\n");
599 void dram_init_banksize(void)
601 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
602 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
604 switch (gd->ram_size) {
605 case 0x10000000: /* DDR_16BIT_256MB */
606 gd->bd->bi_dram[0].size = 0x10000000;
607 gd->bd->bi_dram[1].size = 0;
609 case 0x20000000: /* DDR_32BIT_512MB */
610 gd->bd->bi_dram[0].size = 0x20000000;
611 gd->bd->bi_dram[1].size = 0;
614 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
615 gd->bd->bi_dram[0].size = 0x20000000;
616 gd->bd->bi_dram[1].size = 0x20000000;
617 } else { /* DDR_64BIT_1GB */
618 gd->bd->bi_dram[0].size = 0x40000000;
619 gd->bd->bi_dram[1].size = 0;
622 case 0x80000000: /* DDR_64BIT_2GB */
623 gd->bd->bi_dram[0].size = 0x40000000;
624 gd->bd->bi_dram[1].size = 0x40000000;
626 case 0xEFF00000: /* DDR_64BIT_4GB */
627 gd->bd->bi_dram[0].size = 0x70000000;
628 gd->bd->bi_dram[1].size = 0x7FF00000;
635 gd->ram_size = imx_ddr_size();
636 switch (gd->ram_size) {
643 gd->ram_size -= 0x100000;
646 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
653 u32 get_board_rev(void)
655 return cl_eeprom_get_board_rev();
658 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
659 .reg = (struct mxc_uart *)UART4_BASE,
662 U_BOOT_DEVICE(cm_fx6_serial) = {
663 .name = "serial_mxc",
664 .platdata = &cm_fx6_mxc_serial_plat,