3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/pxa-regs.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* ------------------------------------------------------------------------- */
38 /* local prototypes */
39 void set_led (int led, int color);
40 void error_code_halt (int code);
41 int init_sio (int led, unsigned long base);
42 inline void cradle_outb (unsigned short val, unsigned long base,
44 inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
45 inline void sleep (int i);
48 /**********************************************************/
50 /**********************************************************/
58 /**********************************************************/
59 error_code_halt (int code)
60 /**********************************************************/
71 /**********************************************************/
72 led_code (int code, int color)
73 /**********************************************************/
77 code &= 0xf; /* only 4 leds */
79 for (i = 0; i < 4; i++) {
80 if (code & (1 << i)) {
89 /**********************************************************/
90 set_led (int led, int color)
91 /**********************************************************/
94 unsigned long mask = 0x3 << shift;
96 writel(mask, GPCR2); /* clear bits */
97 writel((color << shift), GPSR2); /* set bits */
102 /**********************************************************/
103 cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
104 /**********************************************************/
106 *(volatile unsigned short *) (base + (reg * 2)) = val;
110 /**********************************************************/
111 cradle_inb (unsigned long base, unsigned long reg)
112 /**********************************************************/
116 val = *(volatile unsigned short *) (base + (reg * 2));
121 /**********************************************************/
122 init_sio (int led, unsigned long base)
123 /**********************************************************/
127 set_led (led, YELLOW);
128 val = cradle_inb (base, CRADLE_SIO_INDEX);
129 val = cradle_inb (base, CRADLE_SIO_INDEX);
135 /* map SCC2 to COM1 */
136 cradle_outb (0x01, base, CRADLE_SIO_INDEX);
137 cradle_outb (0x00, base, CRADLE_SIO_DATA);
139 /* enable SCC2 extended regs */
140 cradle_outb (0x40, base, CRADLE_SIO_INDEX);
141 cradle_outb (0xa0, base, CRADLE_SIO_DATA);
143 /* enable SCC2 clock multiplier */
144 cradle_outb (0x51, base, CRADLE_SIO_INDEX);
145 cradle_outb (0x04, base, CRADLE_SIO_DATA);
148 cradle_outb (0x00, base, CRADLE_SIO_INDEX);
149 cradle_outb (0x04, base, CRADLE_SIO_DATA);
151 /* map SCC2 DMA to channel 0 */
152 cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
153 cradle_outb (0x09, base, CRADLE_SIO_DATA);
155 /* read ID from SIO to check operation */
156 cradle_outb (0xe4, base, 0x3f8 + 0x3);
157 val = cradle_inb (base, 0x3f8 + 0x0);
158 if ((val & 0xf0) != 0x20) {
161 cradle_outb (0, base, CRADLE_SIO_INDEX);
162 cradle_outb (0, base, CRADLE_SIO_DATA);
165 /* set back to bank 0 */
166 cradle_outb (0, base, 0x3f8 + 0x3);
167 set_led (led, GREEN);
172 * Miscelaneous platform dependent initialisations
176 /**********************************************************/
177 board_late_init (void)
178 /**********************************************************/
184 /**********************************************************/
186 /**********************************************************/
188 /* We have RAM, disable cache */
192 led_code (0xf, YELLOW);
194 /* arch number of HHP Cradle */
195 gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
197 /* adress of boot parameters */
198 gd->bd->bi_boot_params = 0xa0000100;
200 /* Init SIOs to enable SCC2 */
201 udelay (100000); /* delay makes it look neat */
202 init_sio (0, CRADLE_SIO1_PHYS);
204 init_sio (1, CRADLE_SIO2_PHYS);
206 init_sio (2, CRADLE_SIO3_PHYS);
213 extern void pxa_dram_init(void);
217 gd->ram_size = PHYS_SDRAM_1_SIZE;
221 void dram_init_banksize(void)
223 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
224 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
227 #ifdef CONFIG_CMD_NET
228 int board_eth_init(bd_t *bis)
231 #ifdef CONFIG_SMC91111
232 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);