3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/sys_proto.h>
31 #include <power/pmic.h>
34 #include "qong_fpga.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 #ifdef CONFIG_HW_WATCHDOG
41 void hw_watchdog_reset(void)
43 mxc_hw_watchdog_reset();
49 /* dram_init must store complete ramsize in gd->ram_size */
50 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
55 static void qong_fpga_reset(void)
57 gpio_set_value(QONG_FPGA_RST_PIN, 0);
59 gpio_set_value(QONG_FPGA_RST_PIN, 1);
64 int board_early_init_f(void)
66 #ifdef CONFIG_QONG_FPGA
67 /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
68 static const struct mxc_weimcs cs1 = {
69 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
70 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
71 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
72 CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
73 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
74 CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
77 mxc_setup_weimcs(1, &cs1);
79 /* setup pins for FPGA */
80 mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
81 mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
82 mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
83 mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
84 mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
88 gpio_direction_output(QONG_FPGA_RST_PIN, 0);
90 /* set interrupt pin as input */
91 gpio_direction_input(QONG_FPGA_IRQ_PIN);
93 /* FPGA JTAG Interface */
94 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
95 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
96 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
97 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
98 gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
99 gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
100 gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
101 gpio_direction_input(QONG_FPGA_TDO_PIN);
104 /* setup pins for UART1 */
105 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
106 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
107 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
108 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
110 /* setup pins for SPI (pmic) */
111 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
112 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
113 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
114 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
115 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
117 /* Setup pins for USB2 Host */
118 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
119 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
120 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
121 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
122 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
123 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
125 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
126 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
128 mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
129 mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
130 mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
131 mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
132 mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
133 mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
134 mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
135 mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
136 mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
137 mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
138 mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
139 mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
141 mx31_set_gpr(MUX_PGP_UH2, 1);
150 /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
151 /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
152 static const struct mxc_weimcs cs0 = {
153 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
154 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
155 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
156 CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
157 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
158 CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
161 mxc_setup_weimcs(0, &cs0);
163 /* board id for linux */
164 gd->bd->bi_arch_number = MACH_TYPE_QONG;
165 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
172 int board_late_init(void)
178 ret = pmic_init(I2C_PMIC);
182 p = pmic_get("FSL_PMIC");
185 /* Enable RTC battery */
186 pmic_reg_read(p, REG_POWER_CTL0, &val);
187 pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
188 pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
190 #ifdef CONFIG_HW_WATCHDOG
191 mxc_hw_watchdog_enable();
199 printf("Board: DAVE/DENX Qong\n");
203 int misc_init_r(void)
205 #ifdef CONFIG_QONG_FPGA
208 tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
210 printf("version register = %u.%u.%u\n",
211 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
216 int board_eth_init(bd_t *bis)
218 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
219 return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
225 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
226 static void board_nand_setup(void)
228 /* CS3: NAND 8-bit */
229 static const struct mxc_weimcs cs3 = {
230 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
231 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
232 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
233 CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
234 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
235 CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
238 mxc_setup_weimcs(3, &cs3);
240 mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
242 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
243 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
244 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
246 /* Make sure to reset the fpga else you cannot access NAND */
249 /* Enable NAND flash */
250 gpio_set_value(15, 1);
251 gpio_set_value(14, 1);
252 gpio_direction_output(15, 0);
253 gpio_direction_input(16);
254 gpio_direction_input(14);
258 int qong_nand_rdy(void *chip)
261 return gpio_get_value(16);
264 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
267 gpio_set_value(15, 0);
269 gpio_set_value(15, 1);
273 void qong_nand_plat_init(void *chip)
275 struct nand_chip *nand = (struct nand_chip *)chip;
276 nand->chip_delay = 20;
277 nand->select_chip = qong_nand_select_chip;
278 nand->options &= ~NAND_BUSWIDTH_16;