2 * Copyright (C) 2009 David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/emif_defs.h>
24 #include <asm/arch/nand_defs.h>
25 #include "../common/misc.h"
28 DECLARE_GLOBAL_DATA_PTR;
31 * With the DM355 EVM, u-boot is *always* a third stage loader,
32 * unless a JTAG debugger handles the first two stages:
34 * - 1st stage is ROM Boot Loader (RBL), which searches for a
35 * second stage loader in one of three places based on SW7:
36 * NAND (with MMC/SD fallback), MMC/SD, or UART.
38 * - 2nd stage is User Boot Loader (UBL), using at most 30KB
39 * of on-chip SRAM, responsible for lowlevel init, and for
40 * loading the third stage loader into DRAM.
42 * - 3rd stage, that's us!
47 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
48 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
50 /* We expect the UBL to have handled "lowlevel init", which
51 * involves setting up at least:
53 * + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
54 * + clock divisors for those PLLs
55 * + LPSC_DDR module enabled
56 * + LPSC_TIMER0 module (still) enabled
58 * + DDR init and timings
59 * + AEMIF timings (for NAND and DM9000)
62 * Some of that is repeated here, mostly as a precaution.
65 /* AEMIF: Some "address" lines are available as GPIOs. A3..A13
66 * could be too if we used A12 as a GPIO during NAND chipselect
67 * (and Linux did too), letting us control the LED on A7/GPIO61.
69 REG(PINMUX2) = 0x0c08;
71 /* UART0 may still be in SyncReset if we didn't boot from UART */
72 davinci_enable_uart0();
74 /* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
75 lpsc_on(DAVINCI_LPSC_TPCC);
76 lpsc_on(DAVINCI_LPSC_TPTC0);
77 lpsc_on(DAVINCI_LPSC_TPTC1);
82 #ifdef CONFIG_NAND_DAVINCI
84 static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
86 struct nand_chip *this = mtd->priv;
87 u32 wbase = (u32) this->IO_ADDR_W;
88 u32 rbase = (u32) this->IO_ADDR_R;
91 __set_bit(14, &wbase);
92 __set_bit(14, &rbase);
94 __clear_bit(14, &wbase);
95 __clear_bit(14, &rbase);
97 this->IO_ADDR_W = (void *)wbase;
98 this->IO_ADDR_R = (void *)rbase;
101 int board_nand_init(struct nand_chip *nand)
103 davinci_nand_init(nand);
104 nand->select_chip = nand_dm355evm_select_chip;