2 * (C) Copyright 2006 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
26 #ifdef CONFIG_NEW_NAND_CODE
29 #include <asm/arch/pxa-regs.h>
32 * not required for Monahans DFC
34 static void delta_hwcontrol(struct mtd_info *mtdinfo, int cmd)
39 /* read device ready pin */
40 static int delta_device_ready(struct mtd_info *mtdinfo)
50 * Write buf to the DFC Controller Data Buffer
52 static void delta_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
54 unsigned long bytes_multi = len & 0xfffffffc;
55 unsigned long rest = len & 0x3;
56 unsigned long *long_buf;
60 for(i=0; i<bytes_multi; i+=4) {
61 long_buf = (unsigned long*) &buf[i];
66 printf("delta_write_buf: ERROR, writing non 4-byte aligned data.\n");
73 * These functions are quite problematic for the DFC. Luckily they are
74 * not used in the current nand code, except for nand_command, which
75 * we've defined our own anyway. The problem is, that we always need
76 * to write 4 bytes to the DFC Data Buffer, but in these functions we
77 * don't know if to buffer the bytes/half words until we've gathered 4
78 * bytes or if to send them straight away.
80 * Solution: Don't use these with Mona's DFC and complain loudly.
82 static void delta_write_word(struct mtd_info *mtd, u16 word)
84 printf("delta_write_word: WARNING, this function does not work with the Monahans DFC!\n");
86 static void delta_write_byte(struct mtd_info *mtd, u_char byte)
88 printf("delta_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
92 * static void delta_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
94 * Shouldn't this be "u_char * const buf" ?
96 static void delta_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
100 /* we have to be carefull not to overflow the buffer if len is
101 * not a multiple of 4 */
102 unsigned long bytes_multi = len & 0xfffffffc;
103 unsigned long rest = len & 0x3;
104 unsigned long *long_buf;
106 /* if there are any, first copy multiple of 4 bytes */
108 for(i=0; i<bytes_multi; i+=4) {
109 long_buf = (unsigned long*) &buf[i];
114 /* ...then the rest */
116 unsigned long rest_data = NDDB;
118 buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
124 static u16 delta_read_word(struct mtd_info *mtd)
126 printf("delta_write_byte: UNIMPLEMENTED.\n");
129 /* global var, too bad: mk@tbd: move to ->priv pointer */
130 static unsigned long read_buf = 0;
131 static unsigned char bytes_read = 0;
133 static u_char delta_read_byte(struct mtd_info *mtd)
135 /* struct nand_chip *this = mtd->priv; */
138 if(bytes_read == 0) {
140 printk("delta_read_byte: 0x%x.\n", read_buf);
142 byte = (unsigned char) (read_buf>>(8 * bytes_read++));
146 printf("delta_read_byte: returning 0x%x.\n", byte);
151 static void wait(unsigned long us)
153 #define OSCR_CLK_FREQ 3.250 /* kHz */
155 unsigned long start = OSCR;
156 unsigned long delta = 0, cur;
161 if(cur < start) /* OSCR overflowed */
162 delta = cur + (start^0xffffffff);
168 /* poll the NAND Controller Status Register for event */
169 static void delta_wait_event(unsigned long event)
182 static unsigned long delta_wait_event2(unsigned long event)
198 /* we don't always wan't to do this */
199 static void delta_new_cmd()
204 /* apparently NDCR[NDRUN] needs to be set before writing to NDCBx */
205 if(!(NDCR & NDCR_ND_RUN)) {
209 if(NDSR & NDSR_WRCMDREQ) {
210 NDSR |= NDSR_WRCMDREQ; /* Ack */
217 static int delta_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
219 /* unsigned long timeo; */
220 unsigned long ndsr=0, event=0;
222 /* mk@tbd set appropriate timeouts */
223 /* if (state == FL_ERASING) */
224 /* timeo = CFG_HZ * 400; */
226 /* timeo = CFG_HZ * 20; */
227 if(state == FL_WRITING) {
228 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
229 } else if(state == FL_ERASING) {
230 event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
233 ndsr = delta_wait_event2(event);
235 if(ndsr & NDSR_CS0_BBD)
236 return(0x1); /* Status Read error */
240 /* this is really monahans, not board specific ... */
241 static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
242 int column, int page_addr)
244 /* register struct nand_chip *this = mtd->priv; */
245 unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
246 unsigned long what_the_hack;
248 /* clear the ugly byte read buffer */
252 /* if command is a double byte cmd, we set bit double cmd bit 19 */
253 /* command2 = (command>>8) & 0xFF; */
254 /* ndcb0 = command | ((command2 ? 1 : 0) << 19); *\/ */
259 ndcb0 = (NAND_CMD_READ0 | (4<<16));
260 column >>= 1; /* adjust for 16 bit bus */
261 ndcb1 = (((column>>1) & 0xff) |
262 ((page_addr<<8) & 0xff00) |
263 ((page_addr<<8) & 0xff0000) |
264 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
267 case NAND_CMD_READID:
269 printk("delta_cmdfunc: NAND_CMD_READID.\n");
270 ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
273 case NAND_CMD_PAGEPROG:
274 /* sent as a multicommand in NAND_CMD_SEQIN */
275 printk("delta_cmdfunc: NAND_CMD_PAGEPROG.\n");
277 case NAND_CMD_ERASE1:
278 printf("delta_cmdfunc: NAND_CMD_ERASE1.\n");
280 ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
281 ndcb1 = (page_addr & 0x00ffffff);
283 case NAND_CMD_ERASE2:
284 printf("delta_cmdfunc: NAND_CMD_ERASE1 empty due to multicmd.\n");
287 /* send PAGE_PROG command(0x1080) */
289 printf("delta_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG.\n");
290 ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
291 column >>= 1; /* adjust for 16 bit bus */
292 ndcb1 = (((column>>1) & 0xff) |
293 ((page_addr<<8) & 0xff00) |
294 ((page_addr<<8) & 0xff0000) |
295 ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
298 /* case NAND_CMD_SEQIN_pointer_operation: */
300 /* /\* This is confusing because the command names are */
301 /* * different compared to the ones in the K9K12Q0C */
302 /* * datasheet. Infact this has nothing to do with */
303 /* * reading, as the but with page programming */
305 /* * Here we send the multibyte commands */
306 /* * cmd1=0x00, cmd2=0x80 (for programming main area) or */
307 /* * cmd1=0x50, cmd2=0x80 (for spare area) */
309 /* * When all data is written to the buffer, the page */
310 /* * program command (0x10) is sent to actually write */
314 /* printf("delta_cmdfunc: NAND_CMD_SEQIN pointer op called.\n"); */
316 /* ndcb0 = (NAND_CMD_SEQIN<<8) | (1<<21) | (1<<19) | (4<<16); */
317 /* if(column >= mtd->oobblock) { */
318 /* /\* OOB area *\/ */
319 /* column -= mtd->oobblock; */
320 /* ndcb0 |= NAND_CMD_READOOB; */
321 /* } else if (column < 256) { */
322 /* /\* First 256 bytes --> READ0 *\/ */
323 /* ndcb0 |= NAND_CMD_READ0; */
325 /* /\* Only for 8 bit devices - not delta!!! *\/ */
327 /* ndcb0 |= NAND_CMD_READ1; */
329 /* event = NDSR_WRDREQ; */
331 case NAND_CMD_STATUS:
332 /* oh, this is not nice. for some reason the real
333 * status byte is in the second read from the data
334 * buffer. The hack is to read the first byte right
335 * here, so the next read access by the nand code
336 * yields the right one.
339 ndcb0 = (NAND_CMD_STATUS | (4<<21));
341 /* #define READ_STATUS_BUG 1 */
342 #ifdef READ_STATUS_BUG
346 delta_wait_event(event);
347 what_the_hack = NDDB;
352 printf("delta_cmdfunc: NAND_CMD_RESET unimplemented.\n");
355 printk("delta_cmdfunc: error, unsupported command.\n");
364 delta_wait_event(event);
369 static void delta_dfc_gpio_init()
371 printf("Setting up DFC GPIO's.\n");
373 /* no idea what is done here, see zylonite.c */
376 DF_ALE_WE1 = 0x00000001;
377 DF_ALE_WE2 = 0x00000001;
378 DF_nCS0 = 0x00000001;
379 DF_nCS1 = 0x00000001;
387 DF_IO10 = 0x00000001;
389 DF_IO11 = 0x00000001;
391 DF_IO12 = 0x00000001;
393 DF_IO13 = 0x00000001;
395 DF_IO14 = 0x00000001;
397 DF_IO15 = 0x00000001;
407 * Board-specific NAND initialization. The following members of the
408 * argument are board-specific (per include/linux/mtd/nand_new.h):
409 * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
410 * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
411 * - hwcontrol: hardwarespecific function for accesing control-lines
412 * - dev_ready: hardwarespecific function for accesing device ready/busy line
413 * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
414 * only be provided if a hardware ECC is available
415 * - eccmode: mode of ecc, see defines
416 * - chip_delay: chip dependent delay for transfering data from array to
418 * - options: various chip options. They can partly be set to inform
419 * nand_scan about special functionality. See the defines for further
421 * Members with a "?" were not set in the merged testing-NAND branch,
422 * so they are not set here either.
424 void board_nand_init(struct nand_chip *nand)
426 unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
428 /* set up GPIO Control Registers */
429 delta_dfc_gpio_init();
431 /* turn on the NAND Controller Clock (104 MHz @ D0) */
432 CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
435 /* printf("stupid loop start...\n"); */
437 /* printf("stupid loop end.\n"); */
440 /* NAND Timing Parameters (in ns) */
441 #define NAND_TIMING_tCH 10
442 #define NAND_TIMING_tCS 0
443 #define NAND_TIMING_tWH 20
444 #define NAND_TIMING_tWP 40
445 /* #define NAND_TIMING_tRH 20 */
446 /* #define NAND_TIMING_tRP 40 */
448 #define NAND_TIMING_tRH 25
449 #define NAND_TIMING_tRP 50
451 #define NAND_TIMING_tR 11123
452 #define NAND_TIMING_tWHR 110
453 #define NAND_TIMING_tAR 10
455 /* Maximum values for NAND Interface Timing Registers in DFC clock
457 #define DFC_MAX_tCH 7
458 #define DFC_MAX_tCS 7
459 #define DFC_MAX_tWH 7
460 #define DFC_MAX_tWP 7
461 #define DFC_MAX_tRH 7
462 #define DFC_MAX_tRP 15
463 #define DFC_MAX_tR 65535
464 #define DFC_MAX_tWHR 15
465 #define DFC_MAX_tAR 15
467 #define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
468 #define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
469 #define MIN(x, y) ((x < y) ? x : y)
472 tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
474 tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
476 tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
478 tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
480 tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
482 tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
484 tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
486 tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
488 tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
492 printf("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
494 /* tRP value is split in the register */
502 NDTR0CS0 = (tCH << 19) |
510 NDTR1CS0 = (tR << 16) |
516 /* If it doesn't work (unlikely) think about:
518 * - chip select don't care
519 * - read id byte count
521 * Intentionally enabled by not setting bits:
524 * - cs don't care, see if we can enable later!
525 * - row address start position (after second cycle)
526 * - pages per block = 32
527 * - ND_RDY : clears command buffer
529 /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
531 NDCR = (NDCR_SPARE_EN | /* use the spare area */
532 NDCR_DWIDTH_C | /* 16bit DFC data bus width */
533 NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
534 (7 << 16) | /* read id count = 7 ???? mk@tbd */
535 NDCR_ND_ARB_EN | /* enable bus arbiter */
536 NDCR_RDYM | /* flash device ready ir masked */
537 NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
539 NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
541 NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
543 NDCR_DBERRM | /* double bit error ir masked */
544 NDCR_SBERRM | /* single bit error ir masked */
545 NDCR_WRDREQM | /* write data request ir masked */
546 NDCR_RDDREQM | /* read data request ir masked */
547 NDCR_WRCMDREQM); /* write command request ir masked */
550 /* wait 10 us due to cmd buffer clear reset */
554 nand->hwcontrol = delta_hwcontrol;
555 /* nand->dev_ready = delta_device_ready; */
556 nand->eccmode = NAND_ECC_SOFT;
557 nand->chip_delay = NAND_DELAY_US;
558 nand->options = NAND_BUSWIDTH_16;
559 nand->waitfunc = delta_wait;
560 nand->read_byte = delta_read_byte;
561 nand->write_byte = delta_write_byte;
562 nand->read_word = delta_read_word;
563 nand->write_word = delta_write_word;
564 nand->read_buf = delta_read_buf;
565 nand->write_buf = delta_write_buf;
567 nand->cmdfunc = delta_cmdfunc;
571 #error "U-Boot legacy NAND support not available for delta board."