3 * Graeme Russ, graeme.russ@gmail.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/ic/sc520.h>
30 #ifdef CONFIG_HW_WATCHDOG
36 DECLARE_GLOBAL_DATA_PTR;
38 #undef SC520_CDP_DEBUG
40 #ifdef SC520_CDP_DEBUG
41 #define PRINTF(fmt,args...) printf (fmt ,##args)
43 #define PRINTF(fmt,args...)
46 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
48 static void enet_timer_isr(void);
49 static void enet_toggle_run_led(void);
52 * Miscellaneous platform dependent initializations
54 int board_early_init_f(void)
56 u16 pio_out_cfg = 0x0000;
58 /* Configure General Purpose Bus timing */
59 writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
60 writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
61 writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
62 writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
63 writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
64 writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
65 writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
67 /* Configure Programmable Input/Output Pins */
68 writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
69 writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
70 writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
71 writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
72 writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
73 writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
77 * Set StrataFlash chips to 16-bit width
78 * Set StrataFlash chips to normal (non reset/power down) mode
80 pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
81 pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
82 pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
83 pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
84 writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
86 /* Turn off auxiliary power output */
87 writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
89 /* Clear FPGA program mode */
90 writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
92 /* Configure Programmable Address Regions */
93 writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
94 writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
95 writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
96 writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
97 writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
98 writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]);
99 writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]);
100 writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
101 writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
102 writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
103 writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
104 writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
105 /* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
106 /* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
108 /* Disable Watchdog */
109 writew(0x3333, &sc520_mmcr->wdtmrctl);
110 writew(0xcccc, &sc520_mmcr->wdtmrctl);
111 writew(0x0000, &sc520_mmcr->wdtmrctl);
113 /* Chip Select Configuration */
114 writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
115 writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
116 writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
118 writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
119 writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
120 writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
122 writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
123 writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
125 /* enable posted-writes */
126 writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
131 int board_early_init_r(void)
133 /* CPU Speed to 100MHz */
134 gd->cpu_clk = 100000000;
136 /* Crystal is 33.000MHz */
137 gd->bus_clk = 33000000;
148 void show_boot_progress(int val)
155 led_mask |= LED_ERR_BITMASK;
157 led_mask |= (uchar)(val & 0x001f);
158 outb(led_mask, LED_LATCH_ADDRESS);
162 int last_stage_init(void)
169 outb(0x00, LED_LATCH_ADDRESS);
171 register_timer_isr (enet_timer_isr);
173 printf("Serck Controls eNET\n");
178 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
180 if (banknum == 0) { /* non-CFI boot flash */
181 info->portwidth = FLASH_CFI_8BIT;
182 info->chipwidth = FLASH_CFI_BY8;
183 info->interface = FLASH_CFI_X8;
189 int board_eth_init(bd_t *bis)
191 return pci_eth_init(bis);
194 void setup_pcat_compatibility()
196 /* disable global interrupt mode */
197 writeb(0x40, &sc520_mmcr->picicr);
199 /* set all irqs to edge */
200 writeb(0x00, &sc520_mmcr->pic_mode[0]);
201 writeb(0x00, &sc520_mmcr->pic_mode[1]);
202 writeb(0x00, &sc520_mmcr->pic_mode[2]);
205 * active low polarity on PIC interrupt pins,
206 * active high polarity on all other irq pins
208 writew(0x0000,&sc520_mmcr->intpinpol);
217 writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
218 writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
219 writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
220 writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
221 writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
223 /* Disable all other interrupt sources */
224 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
225 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
226 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
227 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
228 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
229 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
230 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
231 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
232 writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
235 void enet_timer_isr(void)
237 static long enet_ticks = 0;
241 /* Toggle Watchdog every 100ms */
242 if ((enet_ticks % 100) == 0)
245 /* Toggle Run LED every 500ms */
246 if ((enet_ticks % 500) == 0)
247 enet_toggle_run_led();
250 void hw_watchdog_reset(void)
252 /* Watchdog Reset must be atomic */
253 long flag = disable_interrupts();
255 if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
256 sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
258 sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
264 void enet_toggle_run_led(void)
266 unsigned char leds_state= inb(LED_LATCH_ADDRESS);
267 if (leds_state & LED_RUN_BITMASK)
268 outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
270 outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);