2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
29 static iomux_v3_cfg_t const uart1_pads[] = {
30 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
31 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
34 int board_early_init_f(void)
36 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
41 #ifdef CONFIG_NAND_MXS
43 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
44 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
46 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
48 static iomux_v3_cfg_t const nand_pads[] = {
49 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
50 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
51 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
52 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
53 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
54 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
55 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
56 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
57 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
58 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
59 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
60 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
61 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
62 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
63 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
66 static void setup_gpmi_nand(void)
68 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
70 /* config gpmi nand iomux */
71 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
73 clrbits_le32(&mxc_ccm->CCGR4,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
81 * config gpmi and bch clock to 100 MHz
82 * bch/gpmi select PLL2 PFD2 400M
85 clrbits_le32(&mxc_ccm->cscmr1,
86 MXC_CCM_CSCMR1_BCH_CLK_SEL |
87 MXC_CCM_CSCMR1_GPMI_CLK_SEL);
88 clrsetbits_le32(&mxc_ccm->cscdr1,
89 MXC_CCM_CSCDR1_BCH_PODF_MASK |
90 MXC_CCM_CSCDR1_GPMI_PODF_MASK,
91 (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
92 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
94 /* enable gpmi and bch clock gating */
95 setbits_le32(&mxc_ccm->CCGR4,
96 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
97 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
98 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
99 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
100 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
102 /* enable apbh clock gating */
103 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
105 #endif /* CONFIG_NAND_MXS */
107 #ifdef CONFIG_ENV_IS_IN_MMC
108 static void mmc_late_init(void)
112 u32 dev_no = mmc_get_env_dev();
114 setenv_ulong("mmcdev", dev_no);
117 sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
118 setenv("mmcroot", mmcblk);
120 sprintf(cmd, "mmc dev %d", dev_no);
125 int board_late_init(void)
127 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
131 #ifdef CONFIG_ENV_IS_IN_MMC
134 setenv("modeboot", "mmcboot");
136 case IMX6_BMODE_NAND:
137 setenv("modeboot", "nandboot");
140 setenv("modeboot", "");
149 /* Address of boot parameters */
150 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
152 #ifdef CONFIG_NAND_MXS
161 gd->ram_size = imx_ddr_size();
166 #ifdef CONFIG_SPL_BUILD
170 #include <asm/arch/crm_regs.h>
171 #include <asm/arch/mx6-ddr.h>
173 /* MMC board initialization is needed till adding DM support in SPL */
174 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
176 #include <fsl_esdhc.h>
178 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
179 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
180 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
182 static iomux_v3_cfg_t const usdhc1_pads[] = {
183 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
186 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
187 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
191 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
193 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
195 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
198 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
200 struct fsl_esdhc_cfg usdhc_cfg[1] = {
201 {USDHC1_BASE_ADDR, 0, 4},
204 int board_mmc_getcd(struct mmc *mmc)
206 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
209 switch (cfg->esdhc_base) {
210 case USDHC1_BASE_ADDR:
211 ret = !gpio_get_value(USDHC1_CD_GPIO);
218 int board_mmc_init(bd_t *bis)
223 * According to the board_mmc_init() the following map is done:
224 * (U-boot device node) (Physical Port)
227 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
230 imx_iomux_v3_setup_multiple_pads(
231 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
232 gpio_direction_input(USDHC1_CD_GPIO);
233 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
236 printf("Warning - USDHC%d controller not supporting\n",
241 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
243 printf("Warning: failed to initialize mmc dev %d\n", i);
250 #endif /* CONFIG_FSL_ESDHC */
252 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
253 .grp_addds = 0x00000030,
254 .grp_ddrmode_ctl = 0x00020000,
255 .grp_b0ds = 0x00000030,
256 .grp_ctlds = 0x00000030,
257 .grp_b1ds = 0x00000030,
258 .grp_ddrpke = 0x00000000,
259 .grp_ddrmode = 0x00020000,
260 .grp_ddr_type = 0x000c0000,
263 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
264 .dram_dqm0 = 0x00000030,
265 .dram_dqm1 = 0x00000030,
266 .dram_ras = 0x00000030,
267 .dram_cas = 0x00000030,
268 .dram_odt0 = 0x00000030,
269 .dram_odt1 = 0x00000030,
270 .dram_sdba2 = 0x00000000,
271 .dram_sdclk_0 = 0x00000008,
272 .dram_sdqs0 = 0x00000038,
273 .dram_sdqs1 = 0x00000030,
274 .dram_reset = 0x00000030,
277 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
278 .p0_mpwldectrl0 = 0x00070007,
279 .p0_mpdgctrl0 = 0x41490145,
280 .p0_mprddlctl = 0x40404546,
281 .p0_mpwrdlctl = 0x4040524D,
284 struct mx6_ddr_sysinfo ddr_sysinfo = {
290 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
291 .walat = 1, /* Write additional latency */
292 .ralat = 5, /* Read additional latency */
293 .mif3_mode = 3, /* Command prediction working mode */
294 .bi_on = 1, /* Bank interleaving enabled */
295 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
296 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
297 .ddr_type = DDR_TYPE_DDR3,
300 static struct mx6_ddr3_cfg mem_ddr = {
313 static void ccgr_init(void)
315 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
317 writel(0xFFFFFFFF, &ccm->CCGR0);
318 writel(0xFFFFFFFF, &ccm->CCGR1);
319 writel(0xFFFFFFFF, &ccm->CCGR2);
320 writel(0xFFFFFFFF, &ccm->CCGR3);
321 writel(0xFFFFFFFF, &ccm->CCGR4);
322 writel(0xFFFFFFFF, &ccm->CCGR5);
323 writel(0xFFFFFFFF, &ccm->CCGR6);
324 writel(0xFFFFFFFF, &ccm->CCGR7);
327 static void spl_dram_init(void)
329 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
330 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
333 void board_init_f(ulong dummy)
335 /* setup AIPS and disable watchdog */
340 /* iomux and setup of i2c */
341 board_early_init_f();
346 /* UART clocks enabled and gd valid - init serial console */
347 preloader_console_init();
349 /* DDR initialization */
353 memset(__bss_start, 0, __bss_end - __bss_start);
355 /* load/boot image from boot device */
356 board_init_r(NULL, 0);
358 #endif /* CONFIG_SPL_BUILD */