2 * (C) Copyright 2005-2007
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 extern void lxt971_no_sleep(void);
34 /* fpga configuration data - not compressed, generated by bin2c */
35 const unsigned char fpgadata[] =
39 int filesize = sizeof(fpgadata);
42 int board_early_init_f (void)
45 * IRQ 0-15 405GP internally generated; active high; level sensitive
46 * IRQ 16 405GP internally generated; active low; level sensitive
48 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
49 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
50 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
51 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
52 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
53 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
54 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
56 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
57 mtdcr(uicer, 0x00000000); /* disable all ints */
58 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
59 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
60 mtdcr(uictr, 0x10000000); /* set int trigger levels */
61 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
62 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
65 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
67 mtebc (epcr, 0xa8400000); /* ebc always driven */
70 * Reset CPLD via GPIO12 (CS3) pin
72 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
73 udelay(1000); /* wait 1ms */
74 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
75 udelay(1000); /* wait 1ms */
80 int misc_init_r (void)
82 /* adjust flash start and offset */
83 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
84 gd->bd->bi_flashoffset = 0;
87 * Setup and enable EEPROM write protection
89 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
96 * Check Board Identity:
98 #define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
107 if (getenv_r("serial#", str, sizeof(str)) == -1) {
108 puts ("### No HW ID - assuming CMS700");
113 printf(" (PLD-Version=%02d)\n",
114 in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
119 for (flashcnt = 0; flashcnt < 3; flashcnt++) {
120 out_8((void *)LED_REG, 0x00); /* LEDs off */
121 for (delay = 0; delay < 100; delay++)
123 out_8((void *)LED_REG, 0x0f); /* LEDs on */
124 for (delay = 0; delay < 50; delay++)
127 out_8((void *)LED_REG, 0x70);
132 /* ------------------------------------------------------------------------- */
134 #if defined(CONFIG_SYS_EEPROM_WREN)
135 /* Input: <dev_addr> I2C address of EEPROM device to enable.
136 * <state> -1: deliver current state
139 * Returns: -1: wrong device address
140 * 0: dis-/en- able done
141 * 0/1: current state if <state> was -1.
143 int eeprom_write_enable (unsigned dev_addr, int state)
145 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
150 /* Enable write access, clear bit GPIO_SINT2. */
151 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
155 /* Disable write access, set bit GPIO_SINT2. */
156 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
160 /* Read current status back. */
161 state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
168 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
170 int query = argc == 1;
174 /* Query write access state. */
175 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
177 puts ("Query of write access state failed.\n");
179 printf ("Write access for device 0x%0x is %sabled.\n",
180 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
184 if ('0' == argv[1][0]) {
185 /* Disable write access. */
186 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
188 /* Enable write access. */
189 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
192 puts ("Setup of write access state failed.\n");
199 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
200 "Enable / disable / query EEPROM write access",
202 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
204 /* ------------------------------------------------------------------------- */
208 #ifdef CONFIG_LXT971_NO_SLEEP
211 * Disable sleep mode in LXT971