2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <fdt_support.h>
26 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
36 extern void __ft_board_setup(void *blob, bd_t *bd);
40 /* fpga configuration data - generated by bin2cc */
41 const unsigned char fpgadata[] =
43 #if defined(CONFIG_CPCI405_VER2)
44 # if defined(CONFIG_CPCI405AB)
45 # include "fpgadata_cpci405ab.c"
47 # include "fpgadata_cpci4052.c"
50 # include "fpgadata_cpci405.c"
55 * include common fpga code (for esd boards)
57 #include "../common/fpga.c"
58 #include "../common/auto_update.h"
60 #if defined(CONFIG_CPCI405AB)
61 au_image_t au_image[] = {
62 {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
63 {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
64 {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
65 {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
66 {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
69 #if defined(CONFIG_CPCI405_VER2)
70 au_image_t au_image[] = {
71 {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
72 {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
73 {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
74 {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
75 {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
78 au_image_t au_image[] = {
79 {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
80 {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
81 {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
82 {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
83 {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
88 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
91 int cpci405_version(void);
92 void lxt971_no_sleep(void);
94 int board_early_init_f(void)
96 #ifndef CONFIG_CPCI405_VER2
102 /* set up serial port with default baudrate */
104 gd->baudrate = CONFIG_BAUDRATE;
110 * First pull fpga-prg pin low,
111 * to disable fpga logic (on version 2 board)
113 out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
114 out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
115 out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
116 out_be32((void *)GPIO0_OR, 0); /* pull prg low */
121 #ifndef CONFIG_CPCI405_VER2
122 if (cpci405_version() == 1) {
123 status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
125 /* booting FPGA failed */
127 /* set up serial port with default baudrate */
129 gd->baudrate = CONFIG_BAUDRATE;
133 printf("\nFPGA: Booting failed ");
135 case ERROR_FPGA_PRG_INIT_LOW:
136 printf("(Timeout: INIT not low after "
137 "asserting PROGRAM*)\n ");
139 case ERROR_FPGA_PRG_INIT_HIGH:
140 printf("(Timeout: INIT not high after "
141 "deasserting PROGRAM*)\n ");
143 case ERROR_FPGA_PRG_DONE:
144 printf("(Timeout: DONE not high after "
145 "programming FPGA)\n ");
149 /* display infos on fpgaimage */
151 for (i = 0; i < 4; i++) {
152 len = fpgadata[index];
153 printf("FPGA: %s\n", &(fpgadata[index + 1]));
158 for (i = 20; i > 0; i--) {
159 printf("Rebooting in %2d seconds \r",i);
160 for (index = 0; index < 1000; index++)
164 do_reset(NULL, 0, 0, NULL);
167 #endif /* !CONFIG_CPCI405_VER2 */
170 * IRQ 0-15 405GP internally generated; active high; level sensitive
171 * IRQ 16 405GP internally generated; active low; level sensitive
173 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
174 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
175 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
176 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
177 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
178 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
179 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
181 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
182 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
183 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
184 #if defined(CONFIG_CPCI405_6U)
185 if (cpci405_version() == 3) {
186 mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
188 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
191 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
193 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
194 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
195 * INT0 highest priority */
196 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
203 #if defined(CONFIG_CPCI405_VER2)
204 return 0; /* no, board is cpci405 */
206 if ((in_8((void*)0xf0000400) == 0x00) &&
207 (in_8((void*)0xf0000401) == 0x01))
208 return 0; /* no, board is cpci405 */
210 return -1; /* yes, board is cterm-m2 */
214 int cpci405_host(void)
216 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
217 return -1; /* yes, board is cpci405 host */
219 return 0; /* no, board is cpci405 adapter */
222 int cpci405_version(void)
224 unsigned long CPC0_CR0Reg;
228 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
230 CPC0_CR0Reg = mfdcr(CPC0_CR0);
231 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
232 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
233 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
234 udelay(1000); /* wait some time before reading input */
235 value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
238 * Restore GPIO settings
240 mtdcr(CPC0_CR0, CPC0_CR0Reg);
244 /* CS2==1 && CS3==1 -> version 1 */
247 /* CS2==0 && CS3==1 -> version 2 */
250 /* CS2==1 && CS3==0 -> version 3 or 6U board */
253 /* CS2==0 && CS3==0 -> version 4 */
256 /* should not be reached! */
261 int misc_init_r (void)
263 unsigned long CPC0_CR0Reg;
265 /* adjust flash start and offset */
266 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
267 gd->bd->bi_flashoffset = 0;
269 #if defined(CONFIG_CPCI405_VER2)
272 ulong len = sizeof(fpgadata);
278 * On CPCI-405 version 2 the environment is saved in eeprom!
279 * FPGA can be gzip compressed (malloc) and booted this late.
281 if (cpci405_version() >= 2) {
283 * Setup GPIO pins (CS6+CS7 as GPIO)
285 CPC0_CR0Reg = mfdcr(CPC0_CR0);
286 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
288 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
289 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
290 (uchar *)fpgadata, &len) != 0) {
291 printf("GUNZIP ERROR - must RESET board to recover\n");
292 do_reset(NULL, 0, 0, NULL);
295 status = fpga_boot(dst, len);
297 printf("\nFPGA: Booting failed ");
299 case ERROR_FPGA_PRG_INIT_LOW:
300 printf("(Timeout: INIT not low after "
301 "asserting PROGRAM*)\n ");
303 case ERROR_FPGA_PRG_INIT_HIGH:
304 printf("(Timeout: INIT not high after "
305 "deasserting PROGRAM*)\n ");
307 case ERROR_FPGA_PRG_DONE:
308 printf("(Timeout: DONE not high after "
309 "programming FPGA)\n ");
313 /* display infos on fpgaimage */
315 for (i = 0; i < 4; i++) {
317 printf("FPGA: %s\n", &(dst[index + 1]));
322 for (i = 20; i > 0; i--) {
323 printf("Rebooting in %2d seconds \r", i);
324 for (index = 0; index < 1000; index++)
328 do_reset(NULL, 0, 0, NULL);
331 /* restore gpio/cs settings */
332 mtdcr(CPC0_CR0, CPC0_CR0Reg);
336 /* display infos on fpgaimage */
338 for (i = 0; i < 4; i++) {
340 printf("%s ", &(dst[index + 1]));
348 * Reset FPGA via FPGA_DATA pin
350 SET_FPGA(FPGA_PRG | FPGA_CLK);
351 udelay(1000); /* wait 1ms */
352 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
353 udelay(1000); /* wait 1ms */
355 #if defined(CONFIG_CPCI405_6U)
356 #error HIER GETH ES WEITER MIT IO ACCESSORS
357 if (cpci405_version() == 3) {
359 * Enable outputs in fpga on version 3 board
361 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
362 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
363 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
368 out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
371 * Reset external DUART
373 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
374 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
375 CONFIG_SYS_FPGA_MODE_DUART_RESET);
377 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
378 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
379 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
384 puts("\n*** U-Boot Version does not match Board Version!\n");
385 puts("*** CPCI-405 Version 1.x detected!\n");
386 puts("*** Please use correct U-Boot version "
387 "(CPCI405 instead of CPCI4052)!\n\n");
390 #else /* CONFIG_CPCI405_VER2 */
391 if (cpci405_version() >= 2) {
392 puts("\n*** U-Boot Version does not match Board Version!\n");
393 puts("*** CPCI-405 Board Version 2.x detected!\n");
394 puts("*** Please use correct U-Boot version "
395 "(CPCI4052 instead of CPCI405)!\n\n");
397 #endif /* CONFIG_CPCI405_VER2 */
400 * Select cts (and not dsr) on uart1
402 CPC0_CR0Reg = mfdcr(CPC0_CR0);
403 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
409 * Check Board Identity:
414 #ifndef CONFIG_CPCI405_VER2
419 int i = getenv_r("serial#", str, sizeof(str));
425 puts("### No HW ID - assuming CPCI405");
429 ver = cpci405_version();
430 printf(" (Ver %d.x, ", ver);
436 * Read board-id and save in env-variable
438 sprintf(str, "%d", *(unsigned char *)0xf0000400);
439 setenv("boardid", str);
440 printf("CTERM-M2 - Id=%s)", str);
443 puts("PCI Host Version)");
445 puts("PCI Adapter Version)");
448 #ifndef CONFIG_CPCI405_VER2
451 /* display infos on fpgaimage */
453 for (i = 0; i < 4; i++) {
454 len = fpgadata[index];
455 printf("%s ", &(fpgadata[index + 1]));
466 #if defined(CONFIG_LXT971_NO_SLEEP)
469 * Disable sleep mode in LXT971
475 #if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
476 void ide_set_reset(int on)
479 * Assert or deassert CompactFlash Reset Pin
481 if (on) { /* assert RESET */
482 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
483 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
484 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
485 } else { /* release RESET */
486 out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
487 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
488 CONFIG_SYS_FPGA_MODE_CF_RESET);
492 #endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
494 #if defined(CONFIG_PCI)
495 void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
497 unsigned char int_line = 0xff;
500 * Write pci interrupt line register (cpci405 specific)
502 switch (PCI_DEV(dev) & 0x03) {
517 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
520 int pci_pre_init(struct pci_controller *hose)
522 hose->fixup_irq = cpci405_pci_fixup_irq;
525 #endif /* defined(CONFIG_PCI) */
527 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
528 void ft_board_setup(void *blob, bd_t *bd)
532 __ft_board_setup(blob, bd);
535 * Disable PCI in adapter mode.
537 if (!cpci405_host()) {
538 rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
539 "disabled", sizeof("disabled"), 1);
541 printf("Unable to update property status in PCI node, "
547 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
549 #if defined(CONFIG_CPCI405AB)
550 #define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
551 CONFIG_SYS_FPGA_MODE), \
552 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
553 CONFIG_SYS_FPGA_MODE)) | \
554 CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
556 #define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
557 CONFIG_SYS_FPGA_MODE), \
558 in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
559 CONFIG_SYS_FPGA_MODE)) & \
560 ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
562 #define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
563 CONFIG_SYS_FPGA_STATUS)) & \
564 CONFIG_SYS_FPGA_MODE_1WIRE)
567 * Generate a 1-wire reset, return 1 if no presence detect was found,
568 * return 0 otherwise.
569 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
571 int OWTouchReset(void)
580 result = ONE_WIRE_GET;
587 * Send 1 a 1-wire write bit.
588 * Provide 10us recovery time.
590 void OWWriteBit(int bit)
612 * Read a bit from the 1-wire bus and return it.
613 * Provide 10us recovery time.
624 result = ONE_WIRE_GET;
630 void OWWriteByte(int data)
634 for (loop = 0; loop < 8; loop++) {
635 OWWriteBit(data & 0x01);
642 int loop, result = 0;
644 for (loop = 0; loop < 8; loop++) {
653 int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
658 unsigned char ow_id[6];
660 unsigned char ow_crc;
663 * Clear 1-wire bit (open drain with pull-up)
665 val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
666 CONFIG_SYS_FPGA_MODE));
667 val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
668 out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
669 CONFIG_SYS_FPGA_MODE), val);
671 result = OWTouchReset();
673 puts("No 1-wire device detected!\n");
675 OWWriteByte(0x33); /* send read rom command */
676 OWReadByte(); /* skip family code ( == 0x01) */
677 for (i = 0; i < 6; i++)
678 ow_id[i] = OWReadByte();
679 ow_crc = OWReadByte(); /* read crc */
681 sprintf(str, "%08X%04X",
682 *(unsigned int *)&ow_id[0],
683 *(unsigned short *)&ow_id[4]);
684 printf("Setting environment variable 'ow_id' to %s\n", str);
685 setenv("ow_id", str);
690 onewire, 1, 1, do_onewire,
695 #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
696 #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
699 * Write backplane ip-address...
701 int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
710 buf = malloc(CONFIG_ENV_SIZE_2);
711 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
712 (uchar *)buf, CONFIG_ENV_SIZE_2))
713 puts("\nError reading backplane EEPROM!\n");
715 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
716 if (crc != *(ulong *)buf) {
717 printf("ERROR: crc mismatch %08lx %08lx\n",
725 ptr = strstr(buf+4, "bp_ip=");
727 printf("ERROR: bp_ip not found!\n");
731 ipaddr = string_to_ip(ptr);
734 * Update whole ip-addr
736 bd->bi_ip_addr = ipaddr;
737 sprintf(str, "%ld.%ld.%ld.%ld",
738 (bd->bi_ip_addr & 0xff000000) >> 24,
739 (bd->bi_ip_addr & 0x00ff0000) >> 16,
740 (bd->bi_ip_addr & 0x0000ff00) >> 8,
741 (bd->bi_ip_addr & 0x000000ff));
742 setenv("ipaddr", str);
743 printf("Updated ip_addr from bp_eeprom to %s!\n", str);
751 getbpip, 1, 1, do_get_bpip,
752 "Update IP-Address with Backplane IP-Address",
757 * Set and print backplane ip...
759 int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
770 printf("Setting bp_ip to %s\n", argv[1]);
771 buf = malloc(CONFIG_ENV_SIZE_2);
772 memset(buf, 0, CONFIG_ENV_SIZE_2);
773 sprintf(str, "bp_ip=%s", argv[1]);
775 crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
778 if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
779 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
780 puts("\nError writing backplane EEPROM!\n");
787 setbpip, 2, 1, do_set_bpip,
788 "Write Backplane IP-Address",
792 #endif /* CONFIG_CPCI405AB */