git.sur5r.net Git - u-boot/blob - board/esd/hh405/hh405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <command.h>
  27 #include <malloc.h>
  28
  29 /* ------------------------------------------------------------------------- */
  30
  31 #if 0
  32 #define FPGA_DEBUG
  33 #endif
  34
  35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  36 extern void lxt971_no_sleep(void);
  37
  38 /* fpga configuration data - gzip compressed and generated by bin2c */
  39 const unsigned char fpgadata[] =
  40 {
  41 #include "fpgadata.c"
  42 };
  43
  44 /*
  45  * include common fpga code (for esd boards)
  46  */
  47 #include "../common/fpga.c"
  48
  49
  50 /* Prototypes */
  51 int gunzip(void *, int, unsigned char *, unsigned long *);
  52
  53
  54 /* logo bitmap data - gzip compressed and generated by bin2c */
  55 unsigned char logo_bmp_320[] =
  56 {
  57 #include "logo_320_240_4bpp.c"
  58 };
  59
  60 unsigned char logo_bmp_320_8bpp[] =
  61 {
  62 #include "logo_320_240_8bpp.c"
  63 };
  64
  65 unsigned char logo_bmp_640[] =
  66 {
  67 #include "logo_640_480_24bpp.c"
  68 };
  69
  70 unsigned char logo_bmp_1024[] =
  71 {
  72 #include "logo_1024_768_8bpp.c"
  73 };
  74
  75
  76 /*
  77  * include common lcd code (for esd boards)
  78  */
  79 #include "../common/lcd.c"
  80
  81 #include "../common/s1d13704_320_240_4bpp.h"
  82 #include "../common/s1d13705_320_240_8bpp.h"
  83 #include "../common/s1d13806_640_480_16bpp.h"
  84 #include "../common/s1d13806_1024_768_8bpp.h"
  85
  86
  87 /*
  88  * include common auto-update code (for esd boards)
  89  */
  90 #include "../common/auto_update.h"
  91
  92 au_image_t au_image[] = {
  93         {"hh405/preinst.img", 0, -1, AU_SCRIPT},
  94         {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
  95         {"hh405/pImage_$(bd_type)", 0x00000000, 0x00100000, AU_NAND},
  96         {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
  97         {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
  98         {"hh405/postinst.img", 0, 0, AU_SCRIPT},
  99 };
 100
 101 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 102
 103
 104 int board_revision(void)
 105 {
 106         unsigned long osrh_reg;
 107         unsigned long isr1h_reg;
 108         unsigned long tcr_reg;
 109         unsigned long value;
 110
 111         /*
 112          * Get version of HH405 board from GPIO's
 113          */
 114
 115         /*
 116          * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
 117          */
 118         osrh_reg = in32(GPIO0_OSRH);
 119         isr1h_reg = in32(GPIO0_ISR1H);
 120         tcr_reg = in32(GPIO0_TCR);
 121         out32(GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
 122         out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
 123         out32(GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
 124
 125         udelay(1000);            /* wait some time before reading input */
 126         value = in32(GPIO0_IR) & 0x80400000;         /* get config bits */
 127
 128         /*
 129          * Restore GPIO settings
 130          */
 131         out32(GPIO0_OSRH, osrh_reg);                   /* output select */
 132         out32(GPIO0_ISR1H, isr1h_reg);                 /* input select  */
 133         out32(GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
 134
 135         if (value & 0x80000000) {
 136                 /* Revision 1.0 or 1.1 detected */
 137                 return 1;
 138         } else {
 139                 if (value & 0x00400000) {
 140                         /* Revision 1.3 detected */
 141                         return 3;
 142                 } else {
 143                         /* Revision 1.2 detected */
 144                         return 2;
 145                 }
 146         }
 147 }
 148
 149
 150 int board_early_init_f (void)
 151 {
 152         /*
 153          * IRQ 0-15  405GP internally generated; active high; level sensitive
 154          * IRQ 16    405GP internally generated; active low; level sensitive
 155          * IRQ 17-24 RESERVED
 156          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 157          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 158          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 159          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 160          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 161          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 162          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 163          */
 164         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 165         mtdcr(uicer, 0x00000000);       /* disable all ints */
 166         mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
 167         mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
 168         mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 169         mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 170         mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 171
 172         /*
 173          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
 174          */
 175         mtebc (epcr, 0xa8400000); /* ebc always driven */
 176
 177         return 0;
 178 }
 179
 180
 181 int misc_init_r (void)
 182 {
 183         DECLARE_GLOBAL_DATA_PTR;
 184
 185         volatile unsigned short *fpga_ctrl =
 186                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 187         volatile unsigned short *lcd_contrast =
 188                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
 189         volatile unsigned short *lcd_backlight =
 190                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
 191         unsigned char *dst;
 192         ulong len = sizeof(fpgadata);
 193         int status;
 194         int index;
 195         int i;
 196         char *str;
 197         unsigned long contrast0 = 0xffffffff;
 198
 199         dst = malloc(CFG_FPGA_MAX_SIZE);
 200         if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 201                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 202                 do_reset (NULL, 0, 0, NULL);
 203         }
 204
 205         status = fpga_boot(dst, len);
 206         if (status != 0) {
 207                 printf("\nFPGA: Booting failed ");
 208                 switch (status) {
 209                 case ERROR_FPGA_PRG_INIT_LOW:
 210                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 211                         break;
 212                 case ERROR_FPGA_PRG_INIT_HIGH:
 213                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 214                         break;
 215                 case ERROR_FPGA_PRG_DONE:
 216                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 217                         break;
 218                 }
 219
 220                 /* display infos on fpgaimage */
 221                 index = 15;
 222                 for (i=0; i<4; i++) {
 223                         len = dst[index];
 224                         printf("FPGA: %s\n", &(dst[index+1]));
 225                         index += len+3;
 226                 }
 227                 putc ('\n');
 228                 /* delayed reboot */
 229                 for (i=20; i>0; i--) {
 230                         printf("Rebooting in %2d seconds \r",i);
 231                         for (index=0;index<1000;index++)
 232                                 udelay(1000);
 233                 }
 234                 putc ('\n');
 235                 do_reset(NULL, 0, 0, NULL);
 236         }
 237
 238         puts("FPGA:  ");
 239
 240         /* display infos on fpgaimage */
 241         index = 15;
 242         for (i=0; i<4; i++) {
 243                 len = dst[index];
 244                 printf("%s ", &(dst[index+1]));
 245                 index += len+3;
 246         }
 247         putc ('\n');
 248
 249         free(dst);
 250
 251         /*
 252          * Reset FPGA via FPGA_INIT pin
 253          */
 254         out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
 255         out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 256         udelay(1000); /* wait 1ms */
 257         out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT);   /* reset high */
 258         udelay(1000); /* wait 1ms */
 259
 260         /*
 261          * Write Board revision into FPGA
 262          */
 263         *fpga_ctrl |= gd->board_type & 0x0003;
 264         if (gd->board_type >= 2) {
 265                 *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
 266         }
 267
 268         /*
 269          * Set NAND-FLASH GPIO signals to default
 270          */
 271         out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
 272         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
 273
 274         /*
 275          * Reset touch-screen controller
 276          */
 277         out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
 278         udelay(1000);
 279         out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
 280
 281         /*
 282          * Enable power on PS/2 interface (with reset)
 283          */
 284         *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
 285         for (i=0;i<500;i++)
 286                 udelay(1000);
 287         *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
 288
 289         /*
 290          * Get contrast value from environment variable
 291          */
 292         str = getenv("contrast0");
 293         if (str) {
 294                 contrast0 = simple_strtol(str, NULL, 16);
 295                 if (contrast0 > 255) {
 296                         printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
 297                         contrast0 = 0;
 298                 }
 299         }
 300
 301         /*
 302          * Init lcd interface and display logo
 303          */
 304         str = getenv("bd_type");
 305         if (strcmp(str, "ppc230") == 0) {
 306                 /*
 307                  * Switch backlight on
 308                  */
 309                 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
 310                 *lcd_backlight = 0x0000;
 311
 312                 lcd_setup(1, 0);
 313                 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
 314                          regs_13806_1024_768_8bpp,
 315                          sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
 316                          logo_bmp_1024, sizeof(logo_bmp_1024));
 317         } else if (strcmp(str, "ppc220") == 0) {
 318                 /*
 319                  * Switch backlight on
 320                  */
 321                 *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
 322                 *lcd_backlight = 0x0000;
 323
 324                 lcd_setup(1, 0);
 325                 lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
 326                          regs_13806_640_480_16bpp,
 327                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 328                          logo_bmp_640, sizeof(logo_bmp_640));
 329         } else if (strcmp(str, "ppc215") == 0) {
 330                 /*
 331                  * Set default display contrast voltage
 332                  */
 333                 if (contrast0 == 0xffffffff) {
 334                         *lcd_contrast = 0x0082;
 335                 } else {
 336                         *lcd_contrast = contrast0;
 337                 }
 338                 *lcd_backlight = 0xffff;
 339                 /*
 340                  * Switch backlight on
 341                  */
 342                 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
 343                 /*
 344                  * Set lcd clock (small epson)
 345                  */
 346                 *fpga_ctrl |= LCD_CLK_06250;
 347                 udelay(100);               /* wait for 100 us */
 348
 349                 lcd_setup(0, 1);
 350                 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
 351                          regs_13705_320_240_8bpp,
 352                          sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
 353                          logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
 354         } else if (strcmp(str, "ppc210") == 0) {
 355                 /*
 356                  * Set default display contrast voltage
 357                  */
 358                 if (contrast0 == 0xffffffff) {
 359                         *lcd_contrast = 0x0060;
 360                 } else {
 361                         *lcd_contrast = contrast0;
 362                 }
 363                 *lcd_backlight = 0xffff;
 364                 /*
 365                  * Switch backlight on
 366                  */
 367                 *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
 368                 /*
 369                  * Set lcd clock (small epson)
 370                  */
 371                 *fpga_ctrl |= LCD_CLK_08330;
 372
 373                 lcd_setup(0, 1);
 374                 lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
 375                          regs_13704_320_240_4bpp,
 376                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 377                          logo_bmp_320, sizeof(logo_bmp_320));
 378         } else {
 379                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 380                 return 0;
 381         }
 382
 383         return (0);
 384 }
 385
 386
 387 /*
 388  * Check Board Identity:
 389  */
 390
 391 int checkboard (void)
 392 {
 393         DECLARE_GLOBAL_DATA_PTR;
 394
 395         unsigned char str[64];
 396         int i = getenv_r ("serial#", str, sizeof(str));
 397
 398         puts ("Board: ");
 399
 400         if (i == -1) {
 401                 puts ("### No HW ID - assuming HH405");
 402         } else {
 403                 puts(str);
 404         }
 405
 406         if (getenv_r("bd_type", str, sizeof(str)) != -1) {
 407                 printf(" (%s", str);
 408         } else {
 409                 puts(" (Missing bd_type!");
 410         }
 411
 412         gd->board_type = board_revision();
 413         printf(", Rev 1.%ld)\n", gd->board_type);
 414
 415         /*
 416          * Disable sleep mode in LXT971
 417          */
 418         lxt971_no_sleep();
 419
 420         return 0;
 421 }
 422
 423 /* ------------------------------------------------------------------------- */
 424
 425 long int initdram (int board_type)
 426 {
 427         unsigned long val;
 428
 429         mtdcr(memcfga, mem_mb0cf);
 430         val = mfdcr(memcfgd);
 431
 432 #if 0
 433         printf("\nmb0cf=%x\n", val); /* test-only */
 434         printf("strap=%x\n", mfdcr(strap)); /* test-only */
 435 #endif
 436
 437         return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 438 }
 439
 440 /* ------------------------------------------------------------------------- */
 441
 442 int testdram (void)
 443 {
 444         /* TODO: XXX XXX XXX */
 445         printf ("test: 16 MB - ok\n");
 446
 447         return (0);
 448 }
 449
 450 /* ------------------------------------------------------------------------- */
 451
 452 #ifdef CONFIG_IDE_RESET
 453 void ide_set_reset(int on)
 454 {
 455         volatile unsigned short *fpga_mode =
 456                 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
 457
 458         /*
 459          * Assert or deassert CompactFlash Reset Pin
 460          */
 461         if (on) {               /* assert RESET */
 462                 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
 463         } else {                /* release RESET */
 464                 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
 465         }
 466 }
 467 #endif /* CONFIG_IDE_RESET */
 468
 469
 470 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
 471 #include <linux/mtd/nand.h>
 472 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
 473
 474 void nand_init(void)
 475 {
 476         nand_probe(CFG_NAND_BASE);
 477         if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 478                 print_size(nand_dev_desc[0].totlen, "\n");
 479         }
 480 }
 481 #endif