3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
30 #include <405gp_pci.h>
35 /* ------------------------------------------------------------------------- */
41 /* fpga configuration data - generated by bin2cc */
42 const unsigned char fpgadata[] =
48 * include common fpga code (for esd boards)
50 #include "../common/fpga.c"
54 int gunzip(void *, int, unsigned char *, int *);
57 int board_pre_init (void)
59 unsigned long cntrl0Reg;
62 * IRQ 0-15 405GP internally generated; active high; level sensitive
63 * IRQ 16 405GP internally generated; active low; level sensitive
65 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
66 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
67 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
68 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
69 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
70 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
71 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
73 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
74 mtdcr(uicer, 0x00000000); /* disable all ints */
75 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
76 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
77 mtdcr(uictr, 0x10000000); /* set int trigger levels */
78 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
79 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
82 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
84 cntrl0Reg = mfdcr(cntrl0);
85 mtdcr(cntrl0, cntrl0Reg | 0x00008000);
88 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
90 mtebc (epcr, 0xa8400000); /* ebc always driven */
96 /* ------------------------------------------------------------------------- */
98 int misc_init_f (void)
100 return 0; /* dummy implementation */
104 int misc_init_r (void)
107 ulong len = sizeof(fpgadata);
115 * On PCI-405 the environment is saved in eeprom!
116 * FPGA can be gzip compressed (malloc) and booted this late.
119 dst = malloc(CFG_FPGA_MAX_SIZE);
120 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
121 printf ("GUNZIP ERROR - must RESET board to recover\n");
122 do_reset (NULL, 0, 0, NULL);
125 status = fpga_boot(dst, len);
127 printf("\nFPGA: Booting failed ");
129 case ERROR_FPGA_PRG_INIT_LOW:
130 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
132 case ERROR_FPGA_PRG_INIT_HIGH:
133 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
135 case ERROR_FPGA_PRG_DONE:
136 printf("(Timeout: DONE not high after programming FPGA)\n ");
140 /* display infos on fpgaimage */
142 for (i=0; i<4; i++) {
144 printf("FPGA: %s\n", &(dst[index+1]));
149 for (i=20; i>0; i--) {
150 printf("Rebooting in %2d seconds \r",i);
151 for (index=0;index<1000;index++)
155 do_reset(NULL, 0, 0, NULL);
160 /* display infos on fpgaimage */
162 for (i=0; i<4; i++) {
164 printf("%s ", &(dst[index+1]));
170 * Reset FPGA via FPGA_DATA pin
172 SET_FPGA(FPGA_PRG | FPGA_CLK);
173 udelay(1000); /* wait 1ms */
174 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
175 udelay(1000); /* wait 1ms */
178 * Check if magic for pci reconfig is written
180 magic = (unsigned int *)0x00000004;
181 if (*magic == PCI_RECONFIG_MAGIC) {
183 * Rewrite pci config regs (only after soft-reset with magic set)
185 ptr = (unsigned int *)PCI_REGS_ADDR;
186 if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
187 puts("Restoring PCI Configurations Regs!\n");
188 ptr = (unsigned int *)PCI_REGS_ADDR + 1;
189 for (i=0; i<0x40; i+=4) {
190 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
193 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
195 *magic = 0; /* clear pci reconfig magic again */
204 * Check Board Identity:
207 int checkboard (void)
209 unsigned char str[64];
210 int i = getenv_r ("serial#", str, sizeof(str));
215 puts ("### No HW ID - assuming PCI405");
224 /* ------------------------------------------------------------------------- */
226 long int initdram (int board_type)
230 mtdcr(memcfga, mem_mb0cf);
231 val = mfdcr(memcfgd);
234 printf("\nmb0cf=%x\n", val); /* test-only */
235 printf("strap=%x\n", mfdcr(strap)); /* test-only */
238 #if 0 /* test-only: all PCI405 version must report 16mb */
239 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
241 return (16*1024*1024);
245 /* ------------------------------------------------------------------------- */
249 /* TODO: XXX XXX XXX */
250 printf ("test: 16 MB - ok\n");
255 /* ------------------------------------------------------------------------- */