1 /*------------------------------------------------------------------------------+ */
3 /* This source code has been made available to you by IBM on an AS-IS */
4 /* basis. Anyone receiving this source is licensed under IBM */
5 /* copyrights to use it in any way he or she deems fit, including */
6 /* copying it, modifying it, compiling it, and redistributing it either */
7 /* with or without modifications. No license under IBM patents or */
8 /* patent applications is to be implied by the copyright license. */
10 /* Any user of this software should understand that IBM cannot provide */
11 /* technical support for this software and will not be responsible for */
12 /* any consequences resulting from the use of this software. */
14 /* Any person who transfers this source code or any derivative work */
15 /* must include the IBM copyright notice, this paragraph, and the */
16 /* preceding two paragraphs in the transferred software. */
18 /* COPYRIGHT I B M CORPORATION 1995 */
19 /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
20 /*------------------------------------------------------------------------------- */
22 /*----------------------------------------------------------------------------- */
23 /* Function: ext_bus_cntlr_init */
24 /* Description: Initializes the External Bus Controller for the external */
25 /* peripherals. IMPORTANT: For pass1 this code must run from */
26 /* cache since you can not reliably change a peripheral banks */
27 /* timing register (pbxap) while running code from that bank. */
28 /* For ex., since we are running from ROM on bank 0, we can NOT */
29 /* execute the code that modifies bank 0 timings from ROM, so */
30 /* we run it from cache. */
31 /* Bank 0 - Flash and SRAM */
32 /* Bank 1 - NVRAM/RTC */
33 /* Bank 2 - Keyboard/Mouse controller */
34 /* Bank 3 - IR controller */
35 /* Bank 4 - not used */
36 /* Bank 5 - not used */
37 /* Bank 6 - not used */
38 /* Bank 7 - FPGA registers */
39 /*----------------------------------------------------------------------------- */
42 #include <ppc_asm.tmpl>
45 #include <asm/cache.h>
49 .globl write_without_sync
52 * Write one values to host via pci busmastering
53 * ptr = 0xc0000000 -> 0x01000000 (PCI)
66 * ptr = (volatile unsigned long *)addr;
73 * One pci config write
74 * ibmPciConfigWrite(0x2e, 2, 0x1234);
91 blr /* never reached !!!! */
95 .globl write_with_sync
98 * Write one values to host via pci busmastering
99 * ptr = 0xc0000000 -> 0x01000000 (PCI)
111 * Read one value back
112 * ptr = (volatile unsigned long *)addr;
119 * One pci config write
120 * ibmPciConfigWrite(0x2e, 2, 0x1234);
139 blr /* never reached !!!! */
142 .globl write_with_less_sync
143 write_with_less_sync:
145 * Write one values to host via pci busmastering
146 * ptr = 0xc0000000 -> 0x01000000 (PCI)
158 * Read one value back
159 * ptr = (volatile unsigned long *)addr;
166 * One pci config write
167 * ibmPciConfigWrite(0x2e, 2, 0x1234);
186 blr /* never reached !!!! */
189 .globl write_with_more_sync
190 write_with_more_sync:
192 * Write one values to host via pci busmastering
193 * ptr = 0xc0000000 -> 0x01000000 (PCI)
206 * Read one value back
207 * ptr = (volatile unsigned long *)addr;
215 * One pci config write
216 * ibmPciConfigWrite(0x2e, 2, 0x1234);
218 /* subsystem id (PCIC0_SBSYSVID)*/
235 blr /* never reached !!!! */