2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
36 extern void lxt971_no_sleep(void);
38 /* fpga configuration data - gzip compressed and generated by bin2c */
39 const unsigned char fpgadata[] =
45 * include common fpga code (for esd boards)
47 #include "../common/fpga.c"
50 * include common auto-update code (for esd boards)
52 #include "../common/auto_update.h"
54 au_image_t au_image[] = {
55 {"plu405/preinst.img", 0, -1, AU_SCRIPT},
56 {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
57 {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
58 {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
59 {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
60 {"plu405/postinst.img", 0, 0, AU_SCRIPT},
63 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
66 * generate a short spike on the CAN tx line
67 * to bring the couplers in sync
69 void init_coupler(u32 addr)
71 struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
74 out_8(&ctrl->cr, CR_RR);
77 out_8(&ctrl->btr0, 0x00); /* btr setup is required */
78 out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
79 out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
80 OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
81 out_8(&ctrl->cr, 0x00);
90 out_8(&ctrl->cr, CR_RR);
94 int gunzip(void *, int, unsigned char *, unsigned long *);
96 int board_early_init_f(void)
99 * IRQ 0-15 405GP internally generated; active high; level sensitive
100 * IRQ 16 405GP internally generated; active low; level sensitive
102 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
103 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
104 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
105 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
106 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
107 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
108 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
110 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
111 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
112 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
113 mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
114 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
115 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
116 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
119 * EBC Configuration Register: set ready timeout to
120 * 512 ebc-clks -> ca. 15 us
122 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
127 int misc_init_r(void)
131 ulong len = sizeof(fpgadata);
136 /* adjust flash start and offset */
137 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
138 gd->bd->bi_flashoffset = 0;
140 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
141 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
142 (uchar *)fpgadata, &len) != 0) {
143 printf("GUNZIP ERROR - must RESET board to recover\n");
144 do_reset(NULL, 0, 0, NULL);
147 status = fpga_boot(dst, len);
149 printf("\nFPGA: Booting failed ");
151 case ERROR_FPGA_PRG_INIT_LOW:
152 printf("(Timeout: INIT not low "
153 "after asserting PROGRAM*)\n");
155 case ERROR_FPGA_PRG_INIT_HIGH:
156 printf("(Timeout: INIT not high "
157 "after deasserting PROGRAM*)\n");
159 case ERROR_FPGA_PRG_DONE:
160 printf("(Timeout: DONE not high "
161 "after programming FPGA)\n");
165 /* display infos on fpgaimage */
167 for (i=0; i<4; i++) {
169 printf("FPGA: %s\n", &(dst[index+1]));
174 for (i=20; i>0; i--) {
175 printf("Rebooting in %2d seconds \r",i);
176 for (index=0;index<1000;index++)
180 do_reset(NULL, 0, 0, NULL);
185 /* display infos on fpgaimage */
187 for (i=0; i<4; i++) {
189 printf("%s ", &(dst[index+1]));
197 * Reset FPGA via FPGA_DATA pin
199 SET_FPGA(FPGA_PRG | FPGA_CLK);
200 udelay(1000); /* wait 1ms */
201 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
202 udelay(1000); /* wait 1ms */
205 * Reset external DUARTs
207 out_be32((void*)GPIO0_OR,
208 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
210 out_be32((void*)GPIO0_OR,
211 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
215 * Set NAND-FLASH GPIO signals to default
217 out_be32((void*)GPIO0_OR,
218 in_be32((void*)GPIO0_OR) &
219 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
220 out_be32((void*)GPIO0_OR,
221 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
224 * Setup EEPROM write protection
226 out_be32((void*)GPIO0_OR,
227 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
228 out_be32((void*)GPIO0_TCR,
229 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
232 * Enable interrupts in exar duart mcr[3]
234 out_8((void *)DUART0_BA + 4, 0x08);
235 out_8((void *)DUART1_BA + 4, 0x08);
238 * Enable auto RS485 mode in 2nd external uart
240 out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
241 fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
242 fctr |= 0x08; /* enable RS485 mode */
243 out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
244 out_8((void *)DUART1_BA + 3, 0); /* write LCR */
247 * Init magnetic couplers
249 if (!getenv("noinitcoupler")) {
250 init_coupler(CAN0_BA);
251 init_coupler(CAN1_BA);
257 * Check Board Identity:
262 int i = getenv_r("serial#", str, sizeof(str));
267 puts("### No HW ID - assuming PLU405");
275 #ifdef CONFIG_IDE_RESET
276 #define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
277 void ide_set_reset(int on)
280 * Assert or deassert CompactFlash Reset Pin
282 if (on) { /* assert RESET */
283 out_be16((void *)FPGA_CTRL,
284 in_be16((void *)FPGA_CTRL) &
285 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
286 } else { /* release RESET */
287 out_be16((void *)FPGA_CTRL,
288 in_be16((void *)FPGA_CTRL) |
289 CONFIG_SYS_FPGA_CTRL_CF_RESET);
292 #endif /* CONFIG_IDE_RESET */
296 #ifdef CONFIG_LXT971_NO_SLEEP
299 * Disable sleep mode in LXT971
305 #if defined(CONFIG_SYS_EEPROM_WREN)
306 /* Input: <dev_addr> I2C address of EEPROM device to enable.
307 * <state> -1: deliver current state
310 * Returns: -1: wrong device address
311 * 0: dis-/en- able done
312 * 0/1: current state if <state> was -1.
314 int eeprom_write_enable(unsigned dev_addr, int state)
316 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
321 /* Enable write access, clear bit GPIO0. */
322 out_be32((void*)GPIO0_OR,
323 in_be32((void*)GPIO0_OR) &
324 ~CONFIG_SYS_EEPROM_WP);
328 /* Disable write access, set bit GPIO0. */
329 out_be32((void*)GPIO0_OR,
330 in_be32((void*)GPIO0_OR) |
331 CONFIG_SYS_EEPROM_WP);
335 /* Read current status back. */
336 state = ((in_be32((void*)GPIO0_OR) &
337 CONFIG_SYS_EEPROM_WP) == 0);
344 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
346 int query = argc == 1;
350 /* Query write access state. */
351 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
353 puts("Query of write access state failed.\n");
355 printf("Write access for device 0x%0x is %sabled.\n",
356 CONFIG_SYS_I2C_EEPROM_ADDR,
357 state ? "en" : "dis");
361 if (argv[1][0] == '0') {
362 /* Disable write access. */
363 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
366 /* Enable write access. */
367 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
371 puts("Setup of write access state failed.\n");
377 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
378 "Enable / disable / query EEPROM write access",
381 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */