2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
38 extern void lxt971_no_sleep(void);
40 /* fpga configuration data - gzip compressed and generated by bin2c */
41 const unsigned char fpgadata[] =
47 * include common fpga code (for esd boards)
49 #include "../common/fpga.c"
53 * include common auto-update code (for esd boards)
55 #include "../common/auto_update.h"
57 au_image_t au_image[] = {
58 {"plu405/preinst.img", 0, -1, AU_SCRIPT},
59 {"plu405/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
60 {"plu405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
61 {"plu405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
62 {"plu405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
63 {"plu405/postinst.img", 0, 0, AU_SCRIPT},
66 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
70 int gunzip(void *, int, unsigned char *, unsigned long *);
73 int board_early_init_f (void)
76 * IRQ 0-15 405GP internally generated; active high; level sensitive
77 * IRQ 16 405GP internally generated; active low; level sensitive
79 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
80 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
81 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
82 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
83 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
84 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
85 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
87 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
88 mtdcr(uicer, 0x00000000); /* disable all ints */
89 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
90 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
91 mtdcr(uictr, 0x10000000); /* set int trigger levels */
92 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
93 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
96 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
98 mtebc (epcr, 0xa8400000); /* ebc always driven */
104 int misc_init_f (void)
106 return 0; /* dummy implementation */
110 int misc_init_r (void)
112 volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
113 volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
115 ulong len = sizeof(fpgadata);
120 /* adjust flash start and offset */
121 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
122 gd->bd->bi_flashoffset = 0;
124 dst = malloc(CFG_FPGA_MAX_SIZE);
125 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
126 printf ("GUNZIP ERROR - must RESET board to recover\n");
127 do_reset (NULL, 0, 0, NULL);
130 status = fpga_boot(dst, len);
132 printf("\nFPGA: Booting failed ");
134 case ERROR_FPGA_PRG_INIT_LOW:
135 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
137 case ERROR_FPGA_PRG_INIT_HIGH:
138 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
140 case ERROR_FPGA_PRG_DONE:
141 printf("(Timeout: DONE not high after programming FPGA)\n ");
145 /* display infos on fpgaimage */
147 for (i=0; i<4; i++) {
149 printf("FPGA: %s\n", &(dst[index+1]));
154 for (i=20; i>0; i--) {
155 printf("Rebooting in %2d seconds \r",i);
156 for (index=0;index<1000;index++)
160 do_reset(NULL, 0, 0, NULL);
165 /* display infos on fpgaimage */
167 for (i=0; i<4; i++) {
169 printf("%s ", &(dst[index+1]));
177 * Reset FPGA via FPGA_DATA pin
179 SET_FPGA(FPGA_PRG | FPGA_CLK);
180 udelay(1000); /* wait 1ms */
181 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
182 udelay(1000); /* wait 1ms */
185 * Reset external DUARTs
187 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
188 udelay(10); /* wait 10us */
189 out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
190 udelay(1000); /* wait 1ms */
193 * Enable interrupts in exar duart mcr[3]
203 * Check Board Identity:
205 int checkboard (void)
208 int i = getenv_r ("serial#", str, sizeof(str));
213 puts ("### No HW ID - assuming PLU405");
223 long int initdram (int board_type)
227 mtdcr(memcfga, mem_mb0cf);
228 val = mfdcr(memcfgd);
230 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
234 #ifdef CONFIG_IDE_RESET
235 void ide_set_reset(int on)
237 volatile unsigned short *fpga_mode =
238 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
241 * Assert or deassert CompactFlash Reset Pin
243 if (on) { /* assert RESET */
244 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
245 } else { /* release RESET */
246 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
249 #endif /* CONFIG_IDE_RESET */
254 #ifdef CONFIG_LXT971_NO_SLEEP
257 * Disable sleep mode in LXT971