2 * (C) Copyright 2001-2003
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * (C) Copyright 2005-2009
6 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 extern void lxt971_no_sleep(void);
37 /* fpga configuration data - not compressed, generated by bin2c */
38 const unsigned char fpgadata[] =
42 int filesize = sizeof(fpgadata);
44 int board_early_init_f (void)
47 * IRQ 0-15 405GP internally generated; active high; level sensitive
48 * IRQ 16 405GP internally generated; active low; level sensitive
50 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
51 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
52 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
53 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
54 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
55 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
56 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
58 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
59 mtdcr(uicer, 0x00000000); /* disable all ints */
60 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
61 mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
62 mtdcr(uictr, 0x10000000); /* set int trigger levels */
63 mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
64 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
67 * EBC Configuration Register:
68 * set ready timeout to 512 ebc-clks -> ca. 15 us
70 mtebc (epcr, 0xa8400000);
75 mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT |
76 CONFIG_SYS_FPGA_DONE |
78 CONFIG_SYS_NONMONARCH |
79 CONFIG_SYS_REV1_2) << 5));
81 if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
83 mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE |
84 CONFIG_SYS_SELF_RST) << 5));
87 out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
88 /* setup for output */
89 out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
90 CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
93 * - check if rev1_2 is low, then:
94 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
95 * in TCR to assert INTA# or SELFRST#
100 int misc_init_r (void)
102 /* adjust flash start and offset */
103 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
104 gd->bd->bi_flashoffset = 0;
106 /* deassert EREADY# */
107 out_be32((void *)GPIO0_OR,
108 in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
112 ushort pmc405_pci_subsys_deviceid(void)
116 val = in_be32((void *)GPIO0_IR);
117 if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
118 /* check monarch# signal */
119 if (val & CONFIG_SYS_NONMONARCH)
120 return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
121 return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
123 return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
127 * Check Board Identity
129 int checkboard (void)
133 int i = getenv_r("serial#", str, sizeof(str));
138 puts ("### No HW ID - assuming PMC405");
142 val = in_be32((void *)GPIO0_IR);
143 if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
145 if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
158 #ifdef CONFIG_LXT971_NO_SLEEP
161 * Disable sleep mode in LXT971