2 * (Cg) Copyright 2007-2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on board/amcc/sequoia/sequoia.c
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <fdt_support.h>
32 #include <asm/ppc440.h>
33 #include <asm/processor.h>
35 #include <asm/bitops.h>
38 #ifdef CONFIG_RESET_PHY_R
42 #include <asm/4xx_pci.h>
47 DECLARE_GLOBAL_DATA_PTR;
49 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
50 extern void __ft_board_setup(void *blob, bd_t *bd);
52 ulong flash_get_size(ulong base, int banknum);
53 int pci_is_66mhz(void);
55 int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
56 uchar *buffer, unsigned cnt);
58 struct serial_device *default_serial_console(void)
66 * Use default console on P4 when strapping jumper
67 * is installed (bootstrap option != 'H').
69 mfsdr(SDR0_PINSTP, val);
70 if (((val & 0xf0000000) >> 29) != 7)
71 return &eserial2_device;
73 ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
74 if (!(scratchreg & 0x80)) {
75 /* mark scratchreg valid */
76 scratchreg = (scratchreg & 0xffffff00) | 0x80;
78 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
80 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
83 /* bringup delay for console */
84 for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
89 out_be32((void*)GPIO0_ISR3L, scratchreg);
92 if (scratchreg & 0x01)
93 return &eserial2_device;
95 return &eserial1_device;
98 int board_early_init_f(void)
101 u32 sdr0_pfc1, sdr0_pfc2;
104 /* general EBC configuration (disable EBC timeouts) */
105 mtdcr(EBC0_CFGADDR, EBC0_CFG);
106 mtdcr(EBC0_CFGDATA, 0xf8400000);
109 * Setup the GPIO pins
110 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
112 out_be32((void *)GPIO0_OR, 0x40000102);
113 out_be32((void *)GPIO0_TCR, 0x4c90011f);
114 out_be32((void *)GPIO0_OSRL, 0x28051400);
115 out_be32((void *)GPIO0_OSRH, 0x55005000);
116 out_be32((void *)GPIO0_TSRL, 0x08051400);
117 out_be32((void *)GPIO0_TSRH, 0x55005000);
118 out_be32((void *)GPIO0_ISR1L, 0x54000000);
119 out_be32((void *)GPIO0_ISR1H, 0x00000000);
120 out_be32((void *)GPIO0_ISR2L, 0x44000000);
121 out_be32((void *)GPIO0_ISR2H, 0x00000100);
122 out_be32((void *)GPIO0_ISR3L, 0x00000000);
123 out_be32((void *)GPIO0_ISR3H, 0x00000000);
125 out_be32((void *)GPIO1_OR, 0x80002408);
126 out_be32((void *)GPIO1_TCR, 0xd6003c08);
127 out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
128 out_be32((void *)GPIO1_OSRH, 0x00000000);
129 out_be32((void *)GPIO1_TSRL, 0x00000000);
130 out_be32((void *)GPIO1_TSRH, 0x00000000);
131 out_be32((void *)GPIO1_ISR1L, 0x00005555);
132 out_be32((void *)GPIO1_ISR1H, 0x40000000);
133 out_be32((void *)GPIO1_ISR2L, 0x04010000);
134 out_be32((void *)GPIO1_ISR2H, 0x00000000);
135 out_be32((void *)GPIO1_ISR3L, 0x01400000);
136 out_be32((void *)GPIO1_ISR3H, 0x00000000);
138 /* patch PLB:PCI divider for 66MHz PCI */
139 mfcpr(CPR0_SPCID, reg);
140 if (pci_is_66mhz() && (reg != 0x02000000)) {
141 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
143 mfcpr(CPR0_ICFG, reg);
144 reg |= CPR0_ICFG_RLI_MASK;
145 mtcpr(CPR0_ICFG, reg);
147 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
151 * Setup the interrupt controller polarities, triggers, etc.
153 mtdcr(UIC0SR, 0xffffffff); /* clear all */
154 mtdcr(UIC0ER, 0x00000000); /* disable all */
155 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
156 mtdcr(UIC0PR, 0xfffff7ef);
157 mtdcr(UIC0TR, 0x00000000);
158 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
159 mtdcr(UIC0SR, 0xffffffff); /* clear all */
161 mtdcr(UIC1SR, 0xffffffff); /* clear all */
162 mtdcr(UIC1ER, 0x00000000); /* disable all */
163 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
164 mtdcr(UIC1PR, 0xffffc7f5);
165 mtdcr(UIC1TR, 0x00000000);
166 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
167 mtdcr(UIC1SR, 0xffffffff); /* clear all */
169 mtdcr(UIC2SR, 0xffffffff); /* clear all */
170 mtdcr(UIC2ER, 0x00000000); /* disable all */
171 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
172 mtdcr(UIC2PR, 0x27ffffff);
173 mtdcr(UIC2TR, 0x00000000);
174 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
175 mtdcr(UIC2SR, 0xffffffff); /* clear all */
177 /* select Ethernet pins */
178 mfsdr(SDR0_PFC1, sdr0_pfc1);
179 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
180 SDR0_PFC1_SELECT_CONFIG_4;
181 mfsdr(SDR0_PFC2, sdr0_pfc2);
182 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
183 SDR0_PFC2_SELECT_CONFIG_4;
186 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
188 mtsdr(SDR0_PFC2, sdr0_pfc2);
189 mtsdr(SDR0_PFC1, sdr0_pfc1);
191 /* setup NAND FLASH */
192 mfsdr(SDR0_CUST0, sdr0_cust0);
193 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
194 SDR0_CUST0_NDFC_ENABLE |
195 SDR0_CUST0_NDFC_BW_8_BIT |
196 SDR0_CUST0_NDFC_ARE_MASK |
197 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
198 mtsdr(SDR0_CUST0, sdr0_cust0);
203 #if defined(CONFIG_MISC_INIT_F)
204 int misc_init_f(void)
206 struct pci_controller hose;
207 hose.first_busno = 0;
209 hose.region_count = 0;
211 if (getenv("pciearly") && (!is_monarch())) {
212 printf("PCI: early target init\n");
213 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
214 pci_target_init(&hose);
223 int misc_init_r(void)
228 unsigned long usb2d0cr = 0;
229 unsigned long usb2phy0cr, usb2h0cr = 0;
230 unsigned long sdr0_pfc1;
231 unsigned long sdr0_srst0, sdr0_srst1;
232 char *act = getenv("usbact");
238 /* Re-do sizing to get full correct info */
240 /* adjust flash start and offset */
241 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
242 gd->bd->bi_flashoffset = 0;
244 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
245 mtdcr(EBC0_CFGADDR, PB2CR);
247 mtdcr(EBC0_CFGADDR, PB0CR);
249 pbcr = mfdcr(EBC0_CFGDATA);
250 size_val = ffs(gd->bd->bi_flashsize) - 21;
251 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
252 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
253 mtdcr(EBC0_CFGADDR, PB2CR);
255 mtdcr(EBC0_CFGADDR, PB0CR);
257 mtdcr(EBC0_CFGDATA, pbcr);
260 * Re-check to get correct base address
262 flash_get_size(gd->bd->bi_flashstart, 0);
264 #ifdef CONFIG_ENV_IS_IN_FLASH
265 /* Monitor protection ON by default */
266 (void)flash_protect(FLAG_PROTECT_SET,
267 -CONFIG_SYS_MONITOR_LEN,
271 /* Env protection ON by default */
272 (void)flash_protect(FLAG_PROTECT_SET,
273 CONFIG_ENV_ADDR_REDUND,
274 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
281 if ((act == NULL || strcmp(act, "host") == 0) &&
282 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
284 mfsdr(SDR0_PFC1, sdr0_pfc1);
285 mfsdr(SDR0_USB2D0CR, usb2d0cr);
286 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
287 mfsdr(SDR0_USB2H0CR, usb2h0cr);
289 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
290 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
291 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
292 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
293 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
294 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
295 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
296 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
297 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
298 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
301 * An 8-bit/60MHz interface is the only possible alternative
302 * when connecting the Device to the PHY
304 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
305 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
307 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
308 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
310 mtsdr(SDR0_PFC1, sdr0_pfc1);
311 mtsdr(SDR0_USB2D0CR, usb2d0cr);
312 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
313 mtsdr(SDR0_USB2H0CR, usb2h0cr);
316 * Take USB out of reset:
317 * -Initial status = all cores are in reset
318 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
320 * -deassert reset to PHY
322 * -deassert reset to HOST
324 * -deassert all other resets
326 mfsdr(SDR0_SRST1, sdr0_srst1);
327 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
328 SDR0_SRST1_P4OPB0 | \
330 SDR0_SRST1_PLB42OPB1 | \
331 SDR0_SRST1_OPB2PLB40);
332 mtsdr(SDR0_SRST1, sdr0_srst1);
335 mfsdr(SDR0_SRST1, sdr0_srst1);
336 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
337 mtsdr(SDR0_SRST1, sdr0_srst1);
340 mfsdr(SDR0_SRST0, sdr0_srst0);
341 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
342 mtsdr(SDR0_SRST0, sdr0_srst0);
345 /* finally all the other resets */
346 mtsdr(SDR0_SRST1, 0x00000000);
347 mtsdr(SDR0_SRST0, 0x00000000);
349 if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
350 /* enable power on USB socket */
351 out_be32((void*)GPIO1_OR,
352 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
355 printf("USB: Host\n");
357 } else if ((strcmp(act, "dev") == 0) ||
358 (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
359 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
361 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
362 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
363 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
364 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
365 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
366 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
367 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
368 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
369 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
372 mtsdr(SDR0_SRST1, 0x672c6000);
375 mtsdr(SDR0_SRST0, 0x00000080);
378 mtsdr(SDR0_SRST1, 0x60206000);
380 *(unsigned int *)(0xe0000350) = 0x00000001;
383 mtsdr(SDR0_SRST1, 0x60306000);
386 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
387 mfsdr(SDR0_USB2H0CR, usb2h0cr);
388 mfsdr(SDR0_USB2D0CR, usb2d0cr);
389 mfsdr(SDR0_PFC1, sdr0_pfc1);
391 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
392 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
393 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
394 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
395 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
396 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
397 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
398 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
399 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
400 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
402 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
403 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
405 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
407 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
408 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
410 mtsdr(SDR0_USB2H0CR, usb2h0cr);
411 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
412 mtsdr(SDR0_USB2D0CR, usb2d0cr);
413 mtsdr(SDR0_PFC1, sdr0_pfc1);
417 mtsdr(SDR0_SRST1, 0x00000000);
419 mtsdr(SDR0_SRST0, 0x00000000);
421 printf("USB: Device\n");
425 * Clear PLB4A0_ACR[WRP]
426 * This fix will make the MAL burst disabling patch for the Linux
427 * EMAC driver obsolete.
429 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
430 mtdcr(PLB4A0_ACR, reg);
436 /* turn off POST LED */
437 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
438 /* turn on RUN LED */
439 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
445 if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
451 int pci_is_66mhz(void)
453 if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
458 int board_revision(void)
460 return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
465 puts("Board: esd GmbH - PMC440");
467 gd->board_type = board_revision();
468 printf(", Rev 1.%ld, ", gd->board_type);
474 printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
479 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
481 * Assign interrupts to PCI devices. Some OSs rely on this.
483 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
485 unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
487 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
488 int_line[PCI_DEV(dev) & 0x03]);
495 * The bootstrap configuration provides default settings for the pci
496 * inbound map (PIM). But the bootstrap config choices are limited and
497 * may not be sufficient for a given board.
499 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
500 void pci_target_init(struct pci_controller *hose)
502 char *ptmla_str, *ptmms_str;
505 * Set up Direct MMIO registers
508 * PowerPC440EPX PCI Master configuration.
509 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
510 * PLB address 0x80000000-0xBFFFFFFF
511 * ==> PCI address 0x80000000-0xBFFFFFFF
512 * Use byte reversed out routines to handle endianess.
513 * Make this region non-prefetchable.
515 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
516 /* - disabled b4 setting */
517 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
518 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
519 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
520 out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
521 /* and enable region */
524 ptmla_str = getenv("ptm1la");
525 ptmms_str = getenv("ptm1ms");
526 if(NULL != ptmla_str && NULL != ptmms_str ) {
528 simple_strtoul(ptmms_str, NULL, 16));
530 simple_strtoul(ptmla_str, NULL, 16));
532 /* BAR1: default top 64MB of RAM */
533 out32r(PCIL0_PTM1MS, 0xfc000001);
534 out32r(PCIL0_PTM1LA, 0x0c000000);
537 /* BAR1: default: complete 256MB RAM */
538 out32r(PCIL0_PTM1MS, 0xf0000001);
539 out32r(PCIL0_PTM1LA, 0x00000000);
542 ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
543 ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
544 if(NULL != ptmla_str && NULL != ptmms_str ) {
545 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
546 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
548 /* BAR2: default: 4MB FPGA */
549 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
550 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
554 /* BAR2: map FPGA registers behind system memory at 1GB */
555 pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
559 * Set up Configuration registers
562 /* Program the board's vendor id */
563 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
564 CONFIG_SYS_PCI_SUBSYS_VENDORID);
566 /* disabled for PMC405 backward compatibility */
567 /* Configure command register as bus master */
568 /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
571 /* 240nS PCI clock */
572 pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
574 /* No error reporting */
575 pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
578 /* Program the board's subsystem id/classcode */
579 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
580 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
581 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
582 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
584 /* PCI configuration done: release ERREADY */
585 out_be32((void*)GPIO1_OR,
586 in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
587 out_be32((void*)GPIO1_TCR,
588 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
590 /* Program the board's subsystem id/classcode */
591 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
592 CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
593 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
594 CONFIG_SYS_PCI_CLASSCODE_MONARCH);
597 /* enable host configuration */
598 pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
600 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
603 * Override weak default pci_master_init()
605 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
606 void pci_master_init(struct pci_controller *hose)
609 * Only configure the master in monach mode
612 __pci_master_init(hose);
614 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
616 static void wait_for_pci_ready(void)
618 if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
619 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
625 if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
634 * Override weak is_pci_host()
636 * This routine is called to determine if a pci scan should be
637 * performed. With various hardware environments (especially cPCI and
638 * PPMC) it's insufficient to depend on the state of the arbiter enable
639 * bit in the strap register, or generic host/adapter assumptions.
641 * Rather than hard-code a bad assumption in the general 440 code, the
642 * 440 pci code requires the board to decide at runtime.
644 * Return 0 for adapter mode, non-zero for host (monarch) mode.
646 #if defined(CONFIG_PCI)
647 int is_pci_host(struct pci_controller *hose)
649 char *s = getenv("pciscan");
652 wait_for_pci_ready();
656 else if (!strcmp(s, "yes"))
661 #endif /* defined(CONFIG_PCI) */
663 #ifdef CONFIG_RESET_PHY_R
667 unsigned short val_method, val_behavior;
669 /* special LED setup for NGCC/CANDES */
670 if ((s = getenv("bd_type")) &&
671 ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
673 val_behavior = 0x0cf2;
675 /* PMC440 standard type */
677 val_behavior = 0x0cf0;
680 if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
681 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
682 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
683 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
684 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
687 if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
688 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
689 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
690 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
691 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
696 #if defined(CONFIG_SYS_EEPROM_WREN)
698 * Input: <dev_addr> I2C address of EEPROM device to enable.
699 * <state> -1: deliver current state
702 * Returns: -1: wrong device address
703 * 0: dis-/en- able done
704 * 0/1: current state if <state> was -1.
706 int eeprom_write_enable(unsigned dev_addr, int state)
708 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
709 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
714 /* Enable write access, clear bit GPIO_SINT2. */
715 out_be32((void *)GPIO0_OR,
716 in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
720 /* Disable write access, set bit GPIO_SINT2. */
721 out_be32((void *)GPIO0_OR,
722 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
726 /* Read current status back. */
727 state = (0 == (in_be32((void *)GPIO0_OR)
734 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
736 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
737 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
738 uchar *buffer, unsigned cnt)
740 unsigned end = offset + cnt;
744 #if defined(CONFIG_SYS_EEPROM_WREN)
745 eeprom_write_enable(dev_addr, 1);
748 * Write data until done or would cross a write page boundary.
749 * We must write the address again when changing pages
750 * because the address counter only increments within a page.
753 while (offset < end) {
758 blk_off = offset & 0xFF; /* block offset */
760 addr[0] = offset >> 8; /* block number */
761 addr[1] = blk_off; /* block offset */
763 addr[0] |= dev_addr; /* insert device address */
767 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
768 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
770 maxlen = BOOT_EEPROM_PAGE_SIZE -
771 BOOT_EEPROM_PAGE_OFFSET(blk_off);
772 if (maxlen > I2C_RXTX_LEN)
773 maxlen = I2C_RXTX_LEN;
778 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
784 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
785 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
788 #if defined(CONFIG_SYS_EEPROM_WREN)
789 eeprom_write_enable(dev_addr, 0);
794 int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
795 uchar *buffer, unsigned cnt)
797 unsigned end = offset + cnt;
802 * Read data until done or would cross a page boundary.
803 * We must write the address again when changing pages
804 * because the next page may be in a different device.
806 while (offset < end) {
811 blk_off = offset & 0xFF; /* block offset */
813 addr[0] = offset >> 8; /* block number */
814 addr[1] = blk_off; /* block offset */
817 addr[0] |= dev_addr; /* insert device address */
821 maxlen = 0x100 - blk_off;
822 if (maxlen > I2C_RXTX_LEN)
823 maxlen = I2C_RXTX_LEN;
827 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
836 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
837 int usb_board_init(void)
839 char *act = getenv("usbact");
842 if ((act == NULL || strcmp(act, "host") == 0) &&
843 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
844 /* enable power on USB socket */
845 out_be32((void*)GPIO1_OR,
846 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
848 for (i=0; i<1000; i++)
854 int usb_board_stop(void)
856 /* disable power on USB socket */
857 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
861 int usb_board_init_fail(void)
866 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
868 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
869 void ft_board_setup(void *blob, bd_t *bd)
873 __ft_board_setup(blob, bd);
876 * Disable PCI in non-monarch mode.
879 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
880 "disabled", sizeof("disabled"), 1);
882 printf("Unable to update property status in PCI node, err=%s\n",
887 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */