2 * (Cg) Copyright 2007-2008
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on board/amcc/sequoia/sequoia.c
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <fdt_support.h>
19 #include <asm/ppc440.h>
20 #include <asm/processor.h>
22 #include <asm/bitops.h>
25 #ifdef CONFIG_RESET_PHY_R
29 #include <asm/4xx_pci.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
38 extern void __ft_board_setup(void *blob, bd_t *bd);
40 ulong flash_get_size(ulong base, int banknum);
41 int pci_is_66mhz(void);
43 int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
44 uchar *buffer, unsigned cnt);
46 struct serial_device *default_serial_console(void)
54 * Use default console on P4 when strapping jumper
55 * is installed (bootstrap option != 'H').
57 mfsdr(SDR0_PINSTP, val);
58 if (((val & 0xf0000000) >> 29) != 7)
59 return &eserial2_device;
61 ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
62 if (!(scratchreg & 0x80)) {
63 /* mark scratchreg valid */
64 scratchreg = (scratchreg & 0xffffff00) | 0x80;
66 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
68 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
71 /* bringup delay for console */
72 for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
77 out_be32((void*)GPIO0_ISR3L, scratchreg);
80 if (scratchreg & 0x01)
81 return &eserial2_device;
83 return &eserial1_device;
86 int board_early_init_f(void)
89 u32 sdr0_pfc1, sdr0_pfc2;
92 /* general EBC configuration (disable EBC timeouts) */
93 mtdcr(EBC0_CFGADDR, EBC0_CFG);
94 mtdcr(EBC0_CFGDATA, 0xf8400000);
98 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
100 out_be32((void *)GPIO0_OR, 0x40000102);
101 out_be32((void *)GPIO0_TCR, 0x4c90011f);
102 out_be32((void *)GPIO0_OSRL, 0x28051400);
103 out_be32((void *)GPIO0_OSRH, 0x55005000);
104 out_be32((void *)GPIO0_TSRL, 0x08051400);
105 out_be32((void *)GPIO0_TSRH, 0x55005000);
106 out_be32((void *)GPIO0_ISR1L, 0x54000000);
107 out_be32((void *)GPIO0_ISR1H, 0x00000000);
108 out_be32((void *)GPIO0_ISR2L, 0x44000000);
109 out_be32((void *)GPIO0_ISR2H, 0x00000100);
110 out_be32((void *)GPIO0_ISR3L, 0x00000000);
111 out_be32((void *)GPIO0_ISR3H, 0x00000000);
113 out_be32((void *)GPIO1_OR, 0x80002408);
114 out_be32((void *)GPIO1_TCR, 0xd6003c08);
115 out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
116 out_be32((void *)GPIO1_OSRH, 0x00000000);
117 out_be32((void *)GPIO1_TSRL, 0x00000000);
118 out_be32((void *)GPIO1_TSRH, 0x00000000);
119 out_be32((void *)GPIO1_ISR1L, 0x00005555);
120 out_be32((void *)GPIO1_ISR1H, 0x40000000);
121 out_be32((void *)GPIO1_ISR2L, 0x04010000);
122 out_be32((void *)GPIO1_ISR2H, 0x00000000);
123 out_be32((void *)GPIO1_ISR3L, 0x01400000);
124 out_be32((void *)GPIO1_ISR3H, 0x00000000);
126 /* patch PLB:PCI divider for 66MHz PCI */
127 mfcpr(CPR0_SPCID, reg);
128 if (pci_is_66mhz() && (reg != 0x02000000)) {
129 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
131 mfcpr(CPR0_ICFG, reg);
132 reg |= CPR0_ICFG_RLI_MASK;
133 mtcpr(CPR0_ICFG, reg);
135 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
139 * Setup the interrupt controller polarities, triggers, etc.
141 mtdcr(UIC0SR, 0xffffffff); /* clear all */
142 mtdcr(UIC0ER, 0x00000000); /* disable all */
143 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
144 mtdcr(UIC0PR, 0xfffff7ef);
145 mtdcr(UIC0TR, 0x00000000);
146 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
147 mtdcr(UIC0SR, 0xffffffff); /* clear all */
149 mtdcr(UIC1SR, 0xffffffff); /* clear all */
150 mtdcr(UIC1ER, 0x00000000); /* disable all */
151 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
152 mtdcr(UIC1PR, 0xffffc7f5);
153 mtdcr(UIC1TR, 0x00000000);
154 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
155 mtdcr(UIC1SR, 0xffffffff); /* clear all */
157 mtdcr(UIC2SR, 0xffffffff); /* clear all */
158 mtdcr(UIC2ER, 0x00000000); /* disable all */
159 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
160 mtdcr(UIC2PR, 0x27ffffff);
161 mtdcr(UIC2TR, 0x00000000);
162 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
163 mtdcr(UIC2SR, 0xffffffff); /* clear all */
165 /* select Ethernet pins */
166 mfsdr(SDR0_PFC1, sdr0_pfc1);
167 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
168 SDR0_PFC1_SELECT_CONFIG_4;
169 mfsdr(SDR0_PFC2, sdr0_pfc2);
170 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
171 SDR0_PFC2_SELECT_CONFIG_4;
174 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
176 mtsdr(SDR0_PFC2, sdr0_pfc2);
177 mtsdr(SDR0_PFC1, sdr0_pfc1);
179 /* setup NAND FLASH */
180 mfsdr(SDR0_CUST0, sdr0_cust0);
181 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
182 SDR0_CUST0_NDFC_ENABLE |
183 SDR0_CUST0_NDFC_BW_8_BIT |
184 SDR0_CUST0_NDFC_ARE_MASK |
185 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
186 mtsdr(SDR0_CUST0, sdr0_cust0);
191 #if defined(CONFIG_MISC_INIT_F)
192 int misc_init_f(void)
194 struct pci_controller hose;
195 hose.first_busno = 0;
197 hose.region_count = 0;
199 if (getenv("pciearly") && (!is_monarch())) {
200 printf("PCI: early target init\n");
201 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
202 pci_target_init(&hose);
211 int misc_init_r(void)
216 unsigned long usb2d0cr = 0;
217 unsigned long usb2phy0cr, usb2h0cr = 0;
218 unsigned long sdr0_pfc1;
219 unsigned long sdr0_srst0, sdr0_srst1;
220 char *act = getenv("usbact");
226 /* Re-do sizing to get full correct info */
228 /* adjust flash start and offset */
229 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
230 gd->bd->bi_flashoffset = 0;
232 mtdcr(EBC0_CFGADDR, PB0CR);
233 pbcr = mfdcr(EBC0_CFGDATA);
234 size_val = ffs(gd->bd->bi_flashsize) - 21;
235 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
236 mtdcr(EBC0_CFGADDR, PB0CR);
237 mtdcr(EBC0_CFGDATA, pbcr);
240 * Re-check to get correct base address
242 flash_get_size(gd->bd->bi_flashstart, 0);
244 #ifdef CONFIG_ENV_IS_IN_FLASH
245 /* Monitor protection ON by default */
246 (void)flash_protect(FLAG_PROTECT_SET,
247 -CONFIG_SYS_MONITOR_LEN,
251 /* Env protection ON by default */
252 (void)flash_protect(FLAG_PROTECT_SET,
253 CONFIG_ENV_ADDR_REDUND,
254 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
261 if ((act == NULL || strcmp(act, "host") == 0) &&
262 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
264 mfsdr(SDR0_PFC1, sdr0_pfc1);
265 mfsdr(SDR0_USB2D0CR, usb2d0cr);
266 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
267 mfsdr(SDR0_USB2H0CR, usb2h0cr);
269 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
270 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
271 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
272 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
273 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
274 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
275 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
276 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
277 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
278 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
281 * An 8-bit/60MHz interface is the only possible alternative
282 * when connecting the Device to the PHY
284 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
285 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
287 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
288 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
290 mtsdr(SDR0_PFC1, sdr0_pfc1);
291 mtsdr(SDR0_USB2D0CR, usb2d0cr);
292 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
293 mtsdr(SDR0_USB2H0CR, usb2h0cr);
296 * Take USB out of reset:
297 * -Initial status = all cores are in reset
298 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
300 * -deassert reset to PHY
302 * -deassert reset to HOST
304 * -deassert all other resets
306 mfsdr(SDR0_SRST1, sdr0_srst1);
307 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
308 SDR0_SRST1_P4OPB0 | \
310 SDR0_SRST1_PLB42OPB1 | \
311 SDR0_SRST1_OPB2PLB40);
312 mtsdr(SDR0_SRST1, sdr0_srst1);
315 mfsdr(SDR0_SRST1, sdr0_srst1);
316 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
317 mtsdr(SDR0_SRST1, sdr0_srst1);
320 mfsdr(SDR0_SRST0, sdr0_srst0);
321 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
322 mtsdr(SDR0_SRST0, sdr0_srst0);
325 /* finally all the other resets */
326 mtsdr(SDR0_SRST1, 0x00000000);
327 mtsdr(SDR0_SRST0, 0x00000000);
329 if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
330 /* enable power on USB socket */
331 out_be32((void*)GPIO1_OR,
332 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
335 printf("USB: Host\n");
337 } else if ((strcmp(act, "dev") == 0) ||
338 (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
339 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
341 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
342 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
343 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
344 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
345 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
346 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
347 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
348 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
349 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
352 mtsdr(SDR0_SRST1, 0x672c6000);
355 mtsdr(SDR0_SRST0, 0x00000080);
358 mtsdr(SDR0_SRST1, 0x60206000);
360 *(unsigned int *)(0xe0000350) = 0x00000001;
363 mtsdr(SDR0_SRST1, 0x60306000);
366 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
367 mfsdr(SDR0_USB2H0CR, usb2h0cr);
368 mfsdr(SDR0_USB2D0CR, usb2d0cr);
369 mfsdr(SDR0_PFC1, sdr0_pfc1);
371 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
372 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
373 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
374 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
375 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
376 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
377 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
378 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
379 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
380 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
382 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
383 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
385 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
387 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
388 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
390 mtsdr(SDR0_USB2H0CR, usb2h0cr);
391 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
392 mtsdr(SDR0_USB2D0CR, usb2d0cr);
393 mtsdr(SDR0_PFC1, sdr0_pfc1);
397 mtsdr(SDR0_SRST1, 0x00000000);
399 mtsdr(SDR0_SRST0, 0x00000000);
401 printf("USB: Device\n");
405 * Clear PLB4A0_ACR[WRP]
406 * This fix will make the MAL burst disabling patch for the Linux
407 * EMAC driver obsolete.
409 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
410 mtdcr(PLB4A0_ACR, reg);
416 /* turn off POST LED */
417 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
418 /* turn on RUN LED */
419 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
425 if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
431 int pci_is_66mhz(void)
433 if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
438 int board_revision(void)
440 return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
445 puts("Board: esd GmbH - PMC440");
447 gd->board_type = board_revision();
448 printf(", Rev 1.%ld, ", gd->board_type);
454 printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
459 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
461 * Assign interrupts to PCI devices. Some OSs rely on this.
463 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
465 unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
467 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
468 int_line[PCI_DEV(dev) & 0x03]);
475 * The bootstrap configuration provides default settings for the pci
476 * inbound map (PIM). But the bootstrap config choices are limited and
477 * may not be sufficient for a given board.
479 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
480 void pci_target_init(struct pci_controller *hose)
482 char *ptmla_str, *ptmms_str;
485 * Set up Direct MMIO registers
488 * PowerPC440EPX PCI Master configuration.
489 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
490 * PLB address 0x80000000-0xBFFFFFFF
491 * ==> PCI address 0x80000000-0xBFFFFFFF
492 * Use byte reversed out routines to handle endianess.
493 * Make this region non-prefetchable.
495 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
496 /* - disabled b4 setting */
497 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
498 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
499 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
500 out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
501 /* and enable region */
504 ptmla_str = getenv("ptm1la");
505 ptmms_str = getenv("ptm1ms");
506 if(NULL != ptmla_str && NULL != ptmms_str ) {
508 simple_strtoul(ptmms_str, NULL, 16));
510 simple_strtoul(ptmla_str, NULL, 16));
512 /* BAR1: default top 64MB of RAM */
513 out32r(PCIL0_PTM1MS, 0xfc000001);
514 out32r(PCIL0_PTM1LA, 0x0c000000);
517 /* BAR1: default: complete 256MB RAM */
518 out32r(PCIL0_PTM1MS, 0xf0000001);
519 out32r(PCIL0_PTM1LA, 0x00000000);
522 ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
523 ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
524 if(NULL != ptmla_str && NULL != ptmms_str ) {
525 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
526 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
528 /* BAR2: default: 4MB FPGA */
529 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
530 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
534 /* BAR2: map FPGA registers behind system memory at 1GB */
535 pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
539 * Set up Configuration registers
542 /* Program the board's vendor id */
543 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
544 CONFIG_SYS_PCI_SUBSYS_VENDORID);
546 /* disabled for PMC405 backward compatibility */
547 /* Configure command register as bus master */
548 /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
551 /* 240nS PCI clock */
552 pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
554 /* No error reporting */
555 pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
558 /* Program the board's subsystem id/classcode */
559 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
560 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
561 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
562 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
564 /* PCI configuration done: release ERREADY */
565 out_be32((void*)GPIO1_OR,
566 in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
567 out_be32((void*)GPIO1_TCR,
568 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
570 /* Program the board's subsystem id/classcode */
571 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
572 CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
573 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
574 CONFIG_SYS_PCI_CLASSCODE_MONARCH);
577 /* enable host configuration */
578 pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
580 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
583 * Override weak default pci_master_init()
585 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
586 void pci_master_init(struct pci_controller *hose)
589 * Only configure the master in monach mode
592 __pci_master_init(hose);
594 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
596 static void wait_for_pci_ready(void)
598 if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
599 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
605 if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
614 * Override weak is_pci_host()
616 * This routine is called to determine if a pci scan should be
617 * performed. With various hardware environments (especially cPCI and
618 * PPMC) it's insufficient to depend on the state of the arbiter enable
619 * bit in the strap register, or generic host/adapter assumptions.
621 * Rather than hard-code a bad assumption in the general 440 code, the
622 * 440 pci code requires the board to decide at runtime.
624 * Return 0 for adapter mode, non-zero for host (monarch) mode.
626 #if defined(CONFIG_PCI)
627 int is_pci_host(struct pci_controller *hose)
629 char *s = getenv("pciscan");
632 wait_for_pci_ready();
636 else if (!strcmp(s, "yes"))
641 #endif /* defined(CONFIG_PCI) */
643 #ifdef CONFIG_RESET_PHY_R
647 unsigned short val_method, val_behavior;
649 /* special LED setup for NGCC/CANDES */
650 if ((s = getenv("bd_type")) &&
651 ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
653 val_behavior = 0x0cf2;
655 /* PMC440 standard type */
657 val_behavior = 0x0cf0;
660 if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
661 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
662 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
663 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
664 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
667 if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
668 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
669 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
670 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
671 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
676 #if defined(CONFIG_SYS_EEPROM_WREN)
678 * Input: <dev_addr> I2C address of EEPROM device to enable.
679 * <state> -1: deliver current state
682 * Returns: -1: wrong device address
683 * 0: dis-/en- able done
684 * 0/1: current state if <state> was -1.
686 int eeprom_write_enable(unsigned dev_addr, int state)
688 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
689 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
694 /* Enable write access, clear bit GPIO_SINT2. */
695 out_be32((void *)GPIO0_OR,
696 in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
700 /* Disable write access, set bit GPIO_SINT2. */
701 out_be32((void *)GPIO0_OR,
702 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
706 /* Read current status back. */
707 state = (0 == (in_be32((void *)GPIO0_OR)
714 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
716 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
717 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
718 uchar *buffer, unsigned cnt)
720 unsigned end = offset + cnt;
724 #if defined(CONFIG_SYS_EEPROM_WREN)
725 eeprom_write_enable(dev_addr, 1);
728 * Write data until done or would cross a write page boundary.
729 * We must write the address again when changing pages
730 * because the address counter only increments within a page.
733 while (offset < end) {
738 blk_off = offset & 0xFF; /* block offset */
740 addr[0] = offset >> 8; /* block number */
741 addr[1] = blk_off; /* block offset */
743 addr[0] |= dev_addr; /* insert device address */
747 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
748 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
750 maxlen = BOOT_EEPROM_PAGE_SIZE -
751 BOOT_EEPROM_PAGE_OFFSET(blk_off);
752 if (maxlen > I2C_RXTX_LEN)
753 maxlen = I2C_RXTX_LEN;
758 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
764 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
765 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
768 #if defined(CONFIG_SYS_EEPROM_WREN)
769 eeprom_write_enable(dev_addr, 0);
774 int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
775 uchar *buffer, unsigned cnt)
777 unsigned end = offset + cnt;
782 * Read data until done or would cross a page boundary.
783 * We must write the address again when changing pages
784 * because the next page may be in a different device.
786 while (offset < end) {
791 blk_off = offset & 0xFF; /* block offset */
793 addr[0] = offset >> 8; /* block number */
794 addr[1] = blk_off; /* block offset */
797 addr[0] |= dev_addr; /* insert device address */
801 maxlen = 0x100 - blk_off;
802 if (maxlen > I2C_RXTX_LEN)
803 maxlen = I2C_RXTX_LEN;
807 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
816 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
817 int board_usb_init(int index, enum usb_init_type init)
819 char *act = getenv("usbact");
822 if ((act == NULL || strcmp(act, "host") == 0) &&
823 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
824 /* enable power on USB socket */
825 out_be32((void*)GPIO1_OR,
826 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
828 for (i=0; i<1000; i++)
834 int usb_board_stop(void)
836 /* disable power on USB socket */
837 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
841 int board_usb_cleanup(int index, enum usb_init_type init)
843 return usb_board_stop();
845 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
847 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
848 void ft_board_setup(void *blob, bd_t *bd)
852 __ft_board_setup(blob, bd);
855 * Disable PCI in non-monarch mode.
858 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
859 "disabled", sizeof("disabled"), 1);
861 printf("Unable to update property status in PCI node, err=%s\n",
866 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */