3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * evb64260.c - main board support/init for the Galileo Eval board.
30 #include <galileo/memory.h>
31 #include <galileo/pci.h>
32 #include <galileo/gt64260R.h>
41 extern void zuma_mbox_init(void);
53 /* ------------------------------------------------------------------------- */
55 /* this is the current GT register space location */
56 /* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
58 /* Unfortunately, we cant change it while we are in flash, so we initialize it
59 * to the "final" value. This means that any debug_led calls before
60 * board_pre_init wont work right (like in cpu_init_f).
61 * See also my_remap_gt_regs below. (NTL)
64 unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
66 /* ------------------------------------------------------------------------- */
69 * This is a version of the GT register space remapping function that
70 * doesn't touch globals (meaning, it's ok to run from flash.)
72 * Unfortunately, this has the side effect that a writable
73 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
77 my_remap_gt_regs(u32 cur_loc, u32 new_loc)
81 /* check and see if it's already moved */
82 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
83 if ((temp & 0xffff) == new_loc >> 20)
86 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
87 0xffff0000) | (new_loc >> 20);
89 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
91 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
97 /* move PCI stuff out of the way - NTL */
99 pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE,
100 CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE);
102 pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
103 pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
104 pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
106 pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI,
107 CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE);
110 pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE,
111 CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE);
113 pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
114 pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
115 pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
117 pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI,
118 CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE);
120 /* PCI interface settings */
121 GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
122 GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
123 GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
124 GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
129 /* Setup CPU interface paramaters */
133 cpu_t cpu = get_cpu_type();
136 /* cpu configuration register */
137 tmp = GTREGREAD(CPU_CONFIGURATION);
139 /* set the AACK delay bit
141 tmp |= CPU_CONF_AACK_DELAY;
142 tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
144 /* Galileo claims this is necessary for all busses >= 100 MHz */
145 tmp |= CPU_CONF_FAST_CLK;
147 if (cpu == CPU_750CX) {
148 tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
149 tmp &= ~CPU_CONF_AP_VALID;
151 tmp |= CPU_CONF_DP_VALID;
152 tmp |= CPU_CONF_AP_VALID;
155 /* this only works with the MPX bus */
156 tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
157 tmp |= CPU_CONF_PIPELINE;
158 tmp |= CPU_CONF_TA_DELAY;
160 GT_REG_WRITE(CPU_CONFIGURATION, tmp);
162 /* CPU master control register */
163 tmp = GTREGREAD(CPU_MASTER_CONTROL);
165 tmp |= CPU_MAST_CTL_ARB_EN;
167 if ((cpu == CPU_7400) ||
171 tmp |= CPU_MAST_CTL_CLEAN_BLK;
172 tmp |= CPU_MAST_CTL_FLUSH_BLK;
175 /* cleanblock must be cleared for CPUs
176 * that do not support this command
178 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
179 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
181 GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
187 * set up gal. device mappings, etc.
189 int board_pre_init (void)
194 * set up the GT the way the kernel wants it
195 * the call to move the GT register space will obviously
196 * fail if it has already been done, but we're going to assume
197 * that if it's not at the power-on location, it's where we put
198 * it last time. (huber)
200 my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS);
204 /* mask all external interrupt sources */
205 GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
206 GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
207 GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
208 GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
209 GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
210 GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
211 GT_REG_WRITE(CPU_INT_0_MASK, 0);
212 GT_REG_WRITE(CPU_INT_1_MASK, 0);
213 GT_REG_WRITE(CPU_INT_2_MASK, 0);
214 GT_REG_WRITE(CPU_INT_3_MASK, 0);
216 /* now, onto the configuration */
217 GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG);
219 /* ----- DEVICE BUS SETTINGS ------ */
235 * the dual 7450 module requires burst access to the boot
236 * device, so the serial rom copies the boot device to the
237 * on-board sram on the eval board, and updates the correct
238 * registers to boot from the sram. (device0)
240 #ifdef CONFIG_ZUMA_V2
241 /* Zuma has no SRAM */
244 if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE)
249 memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
251 memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
252 memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
253 memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
255 /* configure device timing */
258 GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
262 GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
265 GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
268 #ifdef CFG_32BIT_BOOT_PAR
269 /* detect if we are booting from the 32 bit flash */
270 if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
271 /* 32 bit boot flash */
272 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
273 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR);
275 /* 8 bit boot flash */
276 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
277 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
280 /* 8 bit boot flash only */
281 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
287 GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0);
288 GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1);
289 GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2);
290 GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3);
292 GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
293 GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX);
298 /* various things to do after relocation */
300 int misc_init_r (void)
311 #ifdef CONFIG_ZUMA_V2
318 after_reloc(ulong dest_addr)
320 DECLARE_GLOBAL_DATA_PTR;
322 /* check to see if we booted from the sram. If so, move things
323 * back to the way they should be. (we're running from main
324 * memory at this point now */
326 if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) {
327 memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
328 memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M);
331 /* now, jump to the main U-Boot board init code */
332 board_init_r ((gd_t *)gd, dest_addr);
337 /* ------------------------------------------------------------------------- */
340 * Check Board Identity:
346 puts ("Board: " CFG_BOARD_NAME "\n");
350 /* utility functions */
352 debug_led(int led, int mode)
354 #ifndef CONFIG_ZUMA_V2
355 volatile int *addr = NULL;
361 addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000);
365 addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000);
369 addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000);
372 } else if (mode == 0) {
375 addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000);
379 addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000);
383 addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000);
389 #endif /* CONFIG_ZUMA_V2 */
393 display_mem_map(void)
396 unsigned int base,size,width;
399 for(i=0;i<=BANK3;i++) {
400 base = memoryGetBankBaseAddress(i);
401 size = memoryGetBankSize(i);
404 printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
408 /* CPU's PCI windows */
409 for(i=0;i<=PCI_HOST1;i++) {
410 printf("\nCPU's PCI %d windows\n", i);
411 base=pciGetSpaceBase(i,PCI_IO);
412 size=pciGetSpaceSize(i,PCI_IO);
413 printf(" IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
414 for(j=0;j<=PCI_REGION3;j++) {
415 base = pciGetSpaceBase(i,j);
416 size = pciGetSpaceSize(i,j);
417 printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
423 printf("\nDEVICES\n");
424 for(i=0;i<=DEVICE3;i++) {
425 base = memoryGetDeviceBaseAddress(i);
426 size = memoryGetDeviceSize(i);
427 width= memoryGetDeviceWidth(i) * 8;
428 printf("DEV %d: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
429 i, base, size>>20, width);
433 base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
434 size = memoryGetDeviceSize(BOOT_DEVICE);
435 width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
436 printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
437 base, size>>20, width);