3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* ------------------------------------------------------------------------- */
31 #define _NOT_USED_ 0xFFFFFFFF
33 #if defined(CONFIG_DRAM_50MHZ)
35 static const uint dram_60ns[] =
36 { 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
37 0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_,
38 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
39 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
40 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
41 0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_,
42 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
43 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
44 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
45 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
46 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
47 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
48 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
49 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
50 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
51 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
53 static const uint dram_70ns[] =
54 { 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
55 0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_,
56 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
57 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
58 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
59 0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_,
60 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
62 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
63 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
64 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
67 0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_,
68 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
71 static const uint edo_60ns[] =
72 { 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
73 0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
74 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
75 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
76 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
78 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
79 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
81 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
82 0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
83 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
85 0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
86 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
87 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
89 static const uint edo_70ns[] =
90 { 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
91 0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_,
92 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
93 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
94 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
95 0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
96 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
97 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
98 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
99 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
100 0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_,
101 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
102 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
103 0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_,
104 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
105 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
107 #elif defined(CONFIG_DRAM_25MHZ)
111 static const uint dram_60ns[] =
112 { 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_,
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
115 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
116 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
117 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
118 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
119 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
120 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
121 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
122 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
123 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
124 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
127 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
129 static const uint dram_70ns[] =
130 { 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
131 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
132 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
133 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
134 0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
135 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
136 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
137 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
138 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
139 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
140 0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
141 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
142 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
143 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
144 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
145 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
147 static const uint edo_60ns[] =
148 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
149 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
150 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
151 0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_,
152 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
153 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
154 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
155 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
156 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
157 0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_,
158 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
159 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
160 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
161 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
162 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
163 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
165 static const uint edo_70ns[] =
166 { 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
167 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
168 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
169 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
170 0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
171 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
172 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
173 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
174 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
175 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
176 0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
177 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
178 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
179 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
180 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
181 0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
183 #error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
186 /* ------------------------------------------------------------------------- */
190 * Check Board Identity:
193 #if defined(CONFIG_FADS) && !defined(CONFIG_MPC86xADS)
194 static void checkdboard(void)
196 /* get db type from BCSR 3 */
197 uint k = (*((uint *)BCSR3) >> 24) & 0x3f;
212 puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
224 default : printf("0x%x", k);
227 #endif /* defined(CONFIG_FADS) && !defined(CONFIG_MPC86xADS) */
229 int checkboard (void)
231 /* get revision from BCSR 3 */
232 uint r = (((*((uint *) BCSR3) >> 23) & 1) << 3)
233 | (((*((uint *) BCSR3) >> 19) & 1) << 2)
234 | (((*((uint *) BCSR3) >> 16) & 3));
239 # ifdef CONFIG_MPC86xADS
244 # endif /* !CONFIG_MPC86xADS */
255 printf ("unknown (0x%x)\n", r);
258 #endif /* CONFIG_FADS */
265 puts ("ENG - this board sucks, check the errata, not supported\n");
268 puts ("PILOT - warning, read errata \n");
271 puts ("A - warning, read errata \n");
277 printf ("unknown revision (0x%x)\n", r);
280 #endif /* CONFIG_ADS */
285 /* ------------------------------------------------------------------------- */
286 static long int dram_size (long int *base, long int maxsize)
288 volatile long int *addr=base;
290 ulong save[32]; /* to make test non-destructive */
293 for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
294 addr = base + cnt; /* pointer arith! */
300 /* write 0 to base address */
305 /* check at base address */
306 if ((val = *addr) != 0) {
311 for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
312 addr = base + cnt; /* pointer arith! */
318 return (cnt * sizeof (long));
324 /* ------------------------------------------------------------------------- */
325 static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
327 volatile immap_t *immap = (immap_t *) CFG_IMMR;
328 volatile memctl8xx_t *memctl = &immap->im_memctl;
335 upmconfig (UPMA, (uint *) edo_70ns,
336 sizeof (edo_70ns) / sizeof (uint));
338 upmconfig (UPMA, (uint *) dram_70ns,
339 sizeof (dram_70ns) / sizeof (uint));
346 upmconfig (UPMA, (uint *) edo_60ns,
347 sizeof (edo_60ns) / sizeof (uint));
349 upmconfig (UPMA, (uint *) dram_60ns,
350 sizeof (dram_60ns) / sizeof (uint));
359 memctl->memc_mptpr = 0x0400; /* divide by 16 */
362 case 4: /* 4 Mbyte uses only CS2 */
363 memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
364 memctl->memc_or2 = 0xffc00800; /* 4M */
367 case 8: /* 8 Mbyte uses both CS3 and CS2 */
368 memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
369 memctl->memc_or3 = 0xffc00800; /* 4M */
370 memctl->memc_br3 = 0x00400081 + base;
371 memctl->memc_or2 = 0xffc00800; /* 4M */
374 case 16: /* 16 Mbyte uses only CS2 */
375 #ifdef CONFIG_ADS /* XXX: why PTA=0x60 only in 16M case? - NTL */
376 memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */
378 memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
380 memctl->memc_or2 = 0xff000800; /* 16M */
383 case 32: /* 32 Mbyte uses both CS3 and CS2 */
384 memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
385 memctl->memc_or3 = 0xff000800; /* 16M */
386 memctl->memc_br3 = 0x01000081 + base;
387 memctl->memc_or2 = 0xff000800; /* 16M */
394 memctl->memc_br2 = 0x81 + base; /* use upma */
396 /* if no dimm is inserted, noMbytes is still detected as 8m, so
397 * sanity check top and bottom of memory */
399 *((uint *) BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
401 /* check bytes / 2 because dram_size tests at base+bytes, which
403 if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
404 *((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
411 /* ------------------------------------------------------------------------- */
413 static void _dramdisable(void)
415 volatile immap_t *immap = (immap_t *)CFG_IMMR;
416 volatile memctl8xx_t *memctl = &immap->im_memctl;
418 memctl->memc_br2 = 0x00000000;
419 memctl->memc_br3 = 0x00000000;
421 /* maybe we should turn off upma here or something */
425 /* SDRAM SUPPORT (FADS ONLY) */
427 #if defined(CONFIG_SDRAM_100MHZ)
429 /* ------------------------------------------------------------------------- */
430 /* sdram table by Dan Malek */
432 /* This has the stretched early timing so the 50 MHz
433 * processor can make the 100 MHz timing. This will
434 * work at all processor speeds.
437 #ifdef SDRAM_ALT_INIT_SEQENCE
438 # define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
439 #define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
440 # define SDRAM_MCRVALUE0 0x80808111 /* run upmb cs4 loop 1 addr 0x11 MRS */
441 # define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0 /* ??? why not 0x80808130? */
443 # define SDRAM_MxMR_PTx 195
444 # define UPM_MRS_ADDR 0x11
445 # define UPM_REFRESH_ADDR 0x30 /* or 0x11 if we want to be like above? */
446 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
448 static const uint sdram_table[] =
450 /* single read. (offset 0 in upm RAM) */
451 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
452 0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_,
454 /* burst read. (offset 8 in upm RAM) */
455 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
456 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
459 /* precharge + MRS. (offset 11 in upm RAM) */
460 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
461 0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
463 /* single write. (offset 18 in upm RAM) */
464 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
465 0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
467 /* burst write. (offset 20 in upm RAM) */
468 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
469 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
470 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
471 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
473 /* refresh. (offset 30 in upm RAM) */
474 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
475 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
476 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
478 /* exception. (offset 3c in upm RAM) */
479 0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ };
481 #elif defined(CONFIG_SDRAM_50MHZ)
483 /* ------------------------------------------------------------------------- */
484 /* sdram table stolen from the fads manual */
485 /* for chip MB811171622A-100 */
487 /* this table is for 32-50MHz operation */
488 #ifdef SDRAM_ALT_INIT_SEQENCE
489 # define SDRAM_MBMRVALUE0 0x80802114 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
490 # define SDRAM_MBMRVALUE1 0x80802118 /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */
491 # define SDRAM_MCRVALUE0 0x80808105 /* run upmb cs4 loop 1 addr 0x5 MRS */
492 # define SDRAM_MCRVALUE1 0x80808130 /* run upmb cs4 loop 1 addr 0x30 REFRESH */
493 # define SDRAM_MPTRVALUE 0x400
494 #define SDRAM_MARVALUE 0x88
496 # define SDRAM_MxMR_PTx 128
497 # define UPM_MRS_ADDR 0x5
498 # define UPM_REFRESH_ADDR 0x30
499 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
501 static const uint sdram_table[] =
503 /* single read. (offset 0 in upm RAM) */
504 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
507 /* precharge + MRS. (offset 5 in upm RAM) */
508 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
510 /* burst read. (offset 8 in upm RAM) */
511 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
512 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
513 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
514 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
516 /* single write. (offset 18 in upm RAM) */
517 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
518 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
520 /* burst write. (offset 20 in upm RAM) */
521 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
522 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,
523 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
524 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
526 /* refresh. (offset 30 in upm RAM) */
527 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
528 0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
529 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
531 /* exception. (offset 3c in upm RAM) */
532 0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
534 /* ------------------------------------------------------------------------- */
536 #error SDRAM not correctly configured
538 /* ------------------------------------------------------------------------- */
541 * Memory Periodic Timer Prescaler
544 #define SDRAM_OR4VALUE 0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */
545 #define SDRAM_BR4VALUE 0x000000c1 /* UPMB,base addr or'ed on later */
547 /* ------------------------------------------------------------------------- */
548 #ifdef SDRAM_ALT_INIT_SEQENCE
549 /* ------------------------------------------------------------------------- */
551 static int _initsdram(uint base, uint noMbytes)
553 volatile immap_t *immap = (immap_t *)CFG_IMMR;
554 volatile memctl8xx_t *memctl = &immap->im_memctl;
556 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
558 memctl->memc_mptpr = SDRAM_MPTPRVALUE;
560 /* Configure the refresh (mostly). This needs to be
561 * based upon processor clock speed and optimized to provide
562 * the highest level of performance. For multiple banks,
563 * this time has to be divided by the number of banks.
564 * Although it is not clear anywhere, it appears the
565 * refresh steps through the chip selects for this UPM
566 * on each refresh cycle.
567 * We have to be careful changing
568 * UPM registers after we ask it to run these commands.
571 memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
572 memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */
576 /* Now run the precharge/nop/mrs commands.
579 memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */
580 /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */
583 /* Run 8 refresh cycles */
585 memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/
586 /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
590 memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */
591 memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */
592 /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
596 memctl->memc_mbmr = SDRAM_MBMRVALUE0; /* TLF 4 */
598 memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
599 memctl->memc_br4 = SDRAM_BR4VALUE | base;
604 /* ------------------------------------------------------------------------- */
605 #else /* !SDRAM_ALT_INIT_SEQUENCE */
606 /* ------------------------------------------------------------------------- */
608 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
609 # define MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
610 # define MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
612 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
613 # define MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
614 # define MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
617 * MxMR settings for SDRAM
621 # define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTBE | \
622 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
623 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
625 # define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT) | MBMR_PTAE | \
626 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \
627 MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
629 static int _initsdram(uint base, uint noMbytes)
631 volatile immap_t *immap = (immap_t *)CFG_IMMR;
632 volatile memctl8xx_t *memctl = &immap->im_memctl;
634 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
636 memctl->memc_mptpr = MPTPR_2BK_4K;
637 memctl->memc_mbmr = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
640 memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
641 memctl->memc_br4 = SDRAM_BR4VALUE | base;
643 /* Perform SDRAM initilization */
644 # ifdef UPM_NOP_ADDR /* not currently in UPM table */
646 memctl->memc_mar = 0x00000000;
647 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
648 MCR_MLCF(0) | UPM_NOP_ADDR;
654 # ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
655 /* step 3: precharge */
656 memctl->memc_mar = 0x00000000;
657 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
658 MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
661 /* step 4: refresh */
662 memctl->memc_mar = 0x00000000;
663 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
664 MCR_MLCF(2) | UPM_REFRESH_ADDR;
667 * note: for some reason, the UPM values we are using include
672 memctl->memc_mar = 0x00000088;
673 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
674 MCR_MLCF(1) | UPM_MRS_ADDR;
677 memctl->memc_mar = 0x00000000;
678 memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
679 MCR_MLCF(0) | UPM_NOP_ADDR;
685 memctl->memc_mbmr |= MBMR_PTBE;
688 #endif /* !SDRAM_ALT_INIT_SEQUENCE */
690 /* ------------------------------------------------------------------------- */
692 static void _sdramdisable(void)
694 volatile immap_t *immap = (immap_t *)CFG_IMMR;
695 volatile memctl8xx_t *memctl = &immap->im_memctl;
697 memctl->memc_br4 = 0x00000000;
699 /* maybe we should turn off upmb here or something */
702 /* ------------------------------------------------------------------------- */
704 static int initsdram(uint base, uint *noMbytes)
706 uint m = CFG_SDRAM_SIZE>>20;
708 /* _initsdram needs access to sdram */
709 *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
711 if(!_initsdram(base, m))
718 *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
726 /* SDRAM SUPPORT (FADS ONLY) */
727 #endif /* CONFIG_FADS */
729 long int initdram (int board_type)
731 uint sdramsz = 0; /* size of sdram in Mbytes */
732 uint base = 0; /* base of dram in bytes */
733 uint m = 0; /* size of dram in Mbytes */
737 if (!initsdram (0x00000000, &sdramsz)) {
738 base = sdramsz << 20;
739 printf ("(%u MB SDRAM) ", sdramsz);
743 k = (*((uint *) BCSR2) >> 23) & 0x0f;
746 /* "MCM36100 / MT8D132X" */
751 /* "MCM36800 / MT16D832X" */
755 /* "MCM36400 / MT8D432X" */
759 /* "MCM36200 / MT16D832X ?" */
776 printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
781 /* the FADS is missing this bit, all rams treated as non-edo */
784 s = (*((uint *) BCSR2) >> 27) & 0x01;
787 if (!_draminit (base, m, s, k)) {
788 printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
794 m += sdramsz; /* add sdram size to total */
797 /********************************
798 *DRAM ERROR, HALT PROCESSOR
799 *********************************/
807 /* ------------------------------------------------------------------------- */
811 /* TODO: XXX XXX XXX */
812 printf ("test: 16 MB - ok\n");
818 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
820 #ifdef CFG_PCMCIA_MEM_ADDR
821 volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
824 int pcmcia_init(void)
826 volatile pcmconf8xx_t *pcmp;
827 uint v, slota, slotb;
830 ** Enable the PCMCIA for a Flash card.
832 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
835 pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
836 pcmp->pcmc_por0 = 0xc00ff05d;
839 /* Set all slots to zero by default. */
840 pcmp->pcmc_pgcra = 0;
841 pcmp->pcmc_pgcrb = 0;
843 pcmp->pcmc_pgcra = 0x40;
846 pcmp->pcmc_pgcrb = 0x40;
849 /* enable PCMCIA buffers */
850 *((uint *)BCSR1) &= ~BCSR1_PCCEN;
852 /* Check if any PCMCIA card is plugged in. */
854 slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
855 slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
857 if (!(slota || slotb)) {
858 printf("No card present\n");
860 pcmp->pcmc_pgcra = 0;
863 pcmp->pcmc_pgcrb = 0;
868 printf("Card present (");
872 /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
874 ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
878 #if defined(CONFIG_MPC86x)
879 switch ((pcmp->pcmc_pipr >> 30) & 3)
880 #elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
881 switch ((pcmp->pcmc_pipr >> 14) & 3)
891 v = 3; /* User lower voltage if supported! */
897 printf("5V, 3V and x.xV");
899 v = 3; /* User lower voltage if supported! */
909 printf("; using 3V");
911 ** Enable 3 volt Vcc.
913 *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
914 *((uint *)BCSR1) |= BCSR1_PCCVCC0;
918 printf("; using 5V");
921 ** Enable 5 volt Vcc.
923 *((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
927 ** Enable 5 volt Vcc.
929 *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
930 *((uint *)BCSR1) |= BCSR1_PCCVCC1;
935 *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */
937 printf("; unknown voltage");
941 /* disable pcmcia reset after a while */
946 pcmp->pcmc_pgcra = 0;
948 pcmp->pcmc_pgcrb = 0;
951 /* If you using a real hd you should give a short
953 #ifdef CONFIG_DISK_SPINUP_TIME
954 udelay(CONFIG_DISK_SPINUP_TIME);
960 #endif /* CFG_CMD_PCMCIA */
962 /* ------------------------------------------------------------------------- */
964 #ifdef CFG_PC_IDE_RESET
966 void ide_set_reset(int on)
968 volatile immap_t *immr = (immap_t *)CFG_IMMR;
971 * Configure PC for IDE Reset Pin
973 if (on) { /* assert RESET */
974 immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
975 } else { /* release RESET */
976 immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
979 /* program port pin as GPIO output */
980 immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
981 immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
982 immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
985 #endif /* CFG_PC_IDE_RESET */
986 /* ------------------------------------------------------------------------- */