git.sur5r.net Git - u-boot/blob - board/freescale/ls1021atwr/ls1021atwr.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/immap_ls102xa.h>
  11 #include <asm/arch/ns_access.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/fsl_serdes.h>
  14 #include <asm/arch/ls102xa_stream_id.h>
  15 #include <asm/pcie_layerscape.h>
  16 #include <hwconfig.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <fsl_ifc.h>
  20 #include <netdev.h>
  21 #include <fsl_mdio.h>
  22 #include <tsec.h>
  23 #include <fsl_sec.h>
  24 #include <spl.h>
  25 #ifdef CONFIG_U_QE
  26 #include "../../../drivers/qe/qe.h"
  27 #endif
  28
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define VERSION_MASK            0x00FF
  33 #define BANK_MASK               0x0001
  34 #define CONFIG_RESET            0x1
  35 #define INIT_RESET              0x1
  36
  37 #define CPLD_SET_MUX_SERDES     0x20
  38 #define CPLD_SET_BOOT_BANK      0x40
  39
  40 #define BOOT_FROM_UPPER_BANK    0x0
  41 #define BOOT_FROM_LOWER_BANK    0x1
  42
  43 #define LANEB_SATA              (0x01)
  44 #define LANEB_SGMII1            (0x02)
  45 #define LANEC_SGMII1            (0x04)
  46 #define LANEC_PCIEX1            (0x08)
  47 #define LANED_PCIEX2            (0x10)
  48 #define LANED_SGMII2            (0x20)
  49
  50 #define MASK_LANE_B             0x1
  51 #define MASK_LANE_C             0x2
  52 #define MASK_LANE_D             0x4
  53 #define MASK_SGMII              0x8
  54
  55 #define KEEP_STATUS             0x0
  56 #define NEED_RESET              0x1
  57
  58 #define SOFT_MUX_ON_I2C3_IFC    0x2
  59 #define SOFT_MUX_ON_CAN3_USB2   0x8
  60 #define SOFT_MUX_ON_QE_LCD      0x10
  61
  62 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  63 #define PIN_I2C3_IFC_MUX_IFC    0x1
  64 #define PIN_CAN3_USB2_MUX_USB2  0x0
  65 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  66 #define PIN_QE_LCD_MUX_LCD      0x0
  67 #define PIN_QE_LCD_MUX_QE       0x1
  68
  69 struct cpld_data {
  70         u8 cpld_ver;            /* cpld revision */
  71         u8 cpld_ver_sub;        /* cpld sub revision */
  72         u8 pcba_ver;            /* pcb revision number */
  73         u8 system_rst;          /* reset system by cpld */
  74         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  75         u8 cfg_rcw_src1;        /* Reset config word 1 */
  76         u8 cfg_rcw_src2;        /* Reset config word 2 */
  77         u8 vbank;               /* Flash bank selection Control */
  78         u8 gpio;                /* GPIO for TWR-ELEV */
  79         u8 i2c3_ifc_mux;
  80         u8 mux_spi2;
  81         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  82         u8 qe_lcd_mux;          /* QE and LCD Selection */
  83         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  84         u8 global_rst;          /* reset with init CPLD reg to default */
  85         u8 rev1;                /* Reserved */
  86         u8 rev2;                /* Reserved */
  87 };
  88
  89 #ifndef CONFIG_QSPI_BOOT
  90 static void convert_serdes_mux(int type, int need_reset);
  91
  92 void cpld_show(void)
  93 {
  94         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  95
  96         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
  97                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
  98                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
  99                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 100                in_8(&cpld_data->vbank) & BANK_MASK);
 101
 102 #ifdef CONFIG_DEBUG
 103         printf("soft_mux_on =%x\n",
 104                in_8(&cpld_data->soft_mux_on));
 105         printf("cfg_rcw_src1 =%x\n",
 106                in_8(&cpld_data->cfg_rcw_src1));
 107         printf("cfg_rcw_src2 =%x\n",
 108                in_8(&cpld_data->cfg_rcw_src2));
 109         printf("vbank =%x\n",
 110                in_8(&cpld_data->vbank));
 111         printf("gpio =%x\n",
 112                in_8(&cpld_data->gpio));
 113         printf("i2c3_ifc_mux =%x\n",
 114                in_8(&cpld_data->i2c3_ifc_mux));
 115         printf("mux_spi2 =%x\n",
 116                in_8(&cpld_data->mux_spi2));
 117         printf("can3_usb2_mux =%x\n",
 118                in_8(&cpld_data->can3_usb2_mux));
 119         printf("qe_lcd_mux =%x\n",
 120                in_8(&cpld_data->qe_lcd_mux));
 121         printf("serdes_mux =%x\n",
 122                in_8(&cpld_data->serdes_mux));
 123 #endif
 124 }
 125 #endif
 126
 127 int checkboard(void)
 128 {
 129         puts("Board: LS1021ATWR\n");
 130 #ifndef CONFIG_QSPI_BOOT
 131         cpld_show();
 132 #endif
 133
 134         return 0;
 135 }
 136
 137 unsigned int get_soc_major_rev(void)
 138 {
 139         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 140         unsigned int svr, major;
 141
 142         svr = in_be32(&gur->svr);
 143         major = SVR_MAJ(svr);
 144
 145         return major;
 146 }
 147
 148 void ddrmc_init(void)
 149 {
 150         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 151
 152         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 153
 154         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 155         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 156
 157         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 158         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 159         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 160         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 161         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 162         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 163
 164         out_be32(&ddr->sdram_cfg_2,  DDR_SDRAM_CFG_2);
 165
 166         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 167         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 168
 169         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 170
 171         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 172
 173         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 174         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 175
 176         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 177         out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 178
 179         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 180         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 181
 182         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 183         udelay(1);
 184         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
 185 }
 186
 187 int dram_init(void)
 188 {
 189 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 190         ddrmc_init();
 191 #endif
 192
 193         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 194         return 0;
 195 }
 196
 197 #ifdef CONFIG_FSL_ESDHC
 198 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 199         {CONFIG_SYS_FSL_ESDHC_ADDR},
 200 };
 201
 202 int board_mmc_init(bd_t *bis)
 203 {
 204         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 205
 206         return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 207 }
 208 #endif
 209
 210 #ifdef CONFIG_TSEC_ENET
 211 int board_eth_init(bd_t *bis)
 212 {
 213         struct fsl_pq_mdio_info mdio_info;
 214         struct tsec_info_struct tsec_info[4];
 215         int num = 0;
 216
 217 #ifdef CONFIG_TSEC1
 218         SET_STD_TSEC_INFO(tsec_info[num], 1);
 219         if (is_serdes_configured(SGMII_TSEC1)) {
 220                 puts("eTSEC1 is in sgmii mode.\n");
 221                 tsec_info[num].flags |= TSEC_SGMII;
 222         }
 223         num++;
 224 #endif
 225 #ifdef CONFIG_TSEC2
 226         SET_STD_TSEC_INFO(tsec_info[num], 2);
 227         if (is_serdes_configured(SGMII_TSEC2)) {
 228                 puts("eTSEC2 is in sgmii mode.\n");
 229                 tsec_info[num].flags |= TSEC_SGMII;
 230         }
 231         num++;
 232 #endif
 233 #ifdef CONFIG_TSEC3
 234         SET_STD_TSEC_INFO(tsec_info[num], 3);
 235         num++;
 236 #endif
 237         if (!num) {
 238                 printf("No TSECs initialized\n");
 239                 return 0;
 240         }
 241
 242         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 243         mdio_info.name = DEFAULT_MII_NAME;
 244         fsl_pq_mdio_init(bis, &mdio_info);
 245
 246         tsec_eth_init(bis, tsec_info, num);
 247
 248         return pci_eth_init(bis);
 249 }
 250 #endif
 251
 252 #ifndef CONFIG_QSPI_BOOT
 253 int config_serdes_mux(void)
 254 {
 255         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 256         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 257
 258         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 259         switch (protocol) {
 260         case 0x10:
 261                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 262                 convert_serdes_mux(LANED_PCIEX2 |
 263                                 LANEC_PCIEX1, KEEP_STATUS);
 264                 break;
 265         case 0x20:
 266                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 267                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 268                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 269                 break;
 270         case 0x30:
 271                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 272                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 273                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 274                 break;
 275         case 0x70:
 276                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 277                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 278                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 279                 break;
 280         }
 281
 282         return 0;
 283 }
 284 #endif
 285
 286 #ifndef CONFIG_QSPI_BOOT
 287 int config_board_mux(void)
 288 {
 289         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 290         int conflict_flag;
 291
 292         conflict_flag = 0;
 293         if (hwconfig("i2c3")) {
 294                 conflict_flag++;
 295                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 296                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 297         }
 298
 299         if (hwconfig("ifc")) {
 300                 conflict_flag++;
 301                 /* some signals can not enable simultaneous*/
 302                 if (conflict_flag > 1)
 303                         goto conflict;
 304                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 305                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 306         }
 307
 308         conflict_flag = 0;
 309         if (hwconfig("usb2")) {
 310                 conflict_flag++;
 311                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 312                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 313         }
 314
 315         if (hwconfig("can3")) {
 316                 conflict_flag++;
 317                 /* some signals can not enable simultaneous*/
 318                 if (conflict_flag > 1)
 319                         goto conflict;
 320                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 321                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 322         }
 323
 324         conflict_flag = 0;
 325         if (hwconfig("lcd")) {
 326                 conflict_flag++;
 327                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 328                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 329         }
 330
 331         if (hwconfig("qe")) {
 332                 conflict_flag++;
 333                 /* some signals can not enable simultaneous*/
 334                 if (conflict_flag > 1)
 335                         goto conflict;
 336                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 337                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 338         }
 339
 340         return 0;
 341
 342 conflict:
 343         printf("WARNING: pin conflict! MUX setting may failed!\n");
 344         return 0;
 345 }
 346 #endif
 347
 348 int board_early_init_f(void)
 349 {
 350         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 351         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 352         unsigned int major;
 353
 354 #ifdef CONFIG_TSEC_ENET
 355         out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 356         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 357 #endif
 358
 359 #ifdef CONFIG_FSL_IFC
 360         init_early_memctl_regs();
 361 #endif
 362
 363 #ifdef CONFIG_FSL_DCU_FB
 364         out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
 365 #endif
 366
 367 #ifdef CONFIG_FSL_QSPI
 368         out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 369 #endif
 370
 371         /*
 372          * Enable snoop requests and DVM message requests for
 373          * Slave insterface S4 (A7 core cluster)
 374          */
 375         out_le32(&cci->slave[4].snoop_ctrl,
 376                  CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 377
 378         major = get_soc_major_rev();
 379         if (major == SOC_MAJOR_VER_1_0) {
 380                 /*
 381                  * Set CCI-400 Slave interface S1, S2 Shareable Override
 382                  * Register All transactions are treated as non-shareable
 383                  */
 384                 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 385                 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 386         }
 387
 388         return 0;
 389 }
 390
 391 #ifdef CONFIG_SPL_BUILD
 392 void board_init_f(ulong dummy)
 393 {
 394         /* Clear the BSS */
 395         memset(__bss_start, 0, __bss_end - __bss_start);
 396
 397         get_clocks();
 398
 399         preloader_console_init();
 400
 401         dram_init();
 402
 403         board_init_r(NULL, 0);
 404 }
 405 #endif
 406
 407 #ifdef CONFIG_LS102XA_NS_ACCESS
 408 static struct csu_ns_dev ns_dev[] = {
 409         { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
 410         { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
 411         { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
 412         { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
 413         { CSU_CSLX_OCRAM, CSU_ALL_RW },
 414         { CSU_CSLX_GIC, CSU_ALL_RW },
 415         { CSU_CSLX_PCIE1, CSU_ALL_RW },
 416         { CSU_CSLX_OCRAM2, CSU_ALL_RW },
 417         { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
 418         { CSU_CSLX_PCIE2, CSU_ALL_RW },
 419         { CSU_CSLX_SATA, CSU_ALL_RW },
 420         { CSU_CSLX_USB3, CSU_ALL_RW },
 421         { CSU_CSLX_SERDES, CSU_ALL_RW },
 422         { CSU_CSLX_QDMA, CSU_ALL_RW },
 423         { CSU_CSLX_LPUART2, CSU_ALL_RW },
 424         { CSU_CSLX_LPUART1, CSU_ALL_RW },
 425         { CSU_CSLX_LPUART4, CSU_ALL_RW },
 426         { CSU_CSLX_LPUART3, CSU_ALL_RW },
 427         { CSU_CSLX_LPUART6, CSU_ALL_RW },
 428         { CSU_CSLX_LPUART5, CSU_ALL_RW },
 429         { CSU_CSLX_DSPI2, CSU_ALL_RW },
 430         { CSU_CSLX_DSPI1, CSU_ALL_RW },
 431         { CSU_CSLX_QSPI, CSU_ALL_RW },
 432         { CSU_CSLX_ESDHC, CSU_ALL_RW },
 433         { CSU_CSLX_2D_ACE, CSU_ALL_RW },
 434         { CSU_CSLX_IFC, CSU_ALL_RW },
 435         { CSU_CSLX_I2C1, CSU_ALL_RW },
 436         { CSU_CSLX_USB2, CSU_ALL_RW },
 437         { CSU_CSLX_I2C3, CSU_ALL_RW },
 438         { CSU_CSLX_I2C2, CSU_ALL_RW },
 439         { CSU_CSLX_DUART2, CSU_ALL_RW },
 440         { CSU_CSLX_DUART1, CSU_ALL_RW },
 441         { CSU_CSLX_WDT2, CSU_ALL_RW },
 442         { CSU_CSLX_WDT1, CSU_ALL_RW },
 443         { CSU_CSLX_EDMA, CSU_ALL_RW },
 444         { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
 445         { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
 446         { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
 447         { CSU_CSLX_DDR, CSU_ALL_RW },
 448         { CSU_CSLX_QUICC, CSU_ALL_RW },
 449         { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
 450         { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
 451         { CSU_CSLX_SFP, CSU_ALL_RW },
 452         { CSU_CSLX_TMU, CSU_ALL_RW },
 453         { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
 454         { CSU_CSLX_RESERVED0, CSU_ALL_RW },
 455         { CSU_CSLX_ETSEC1, CSU_ALL_RW },
 456         { CSU_CSLX_SEC5_5, CSU_ALL_RW },
 457         { CSU_CSLX_ETSEC3, CSU_ALL_RW },
 458         { CSU_CSLX_ETSEC2, CSU_ALL_RW },
 459         { CSU_CSLX_GPIO2, CSU_ALL_RW },
 460         { CSU_CSLX_GPIO1, CSU_ALL_RW },
 461         { CSU_CSLX_GPIO4, CSU_ALL_RW },
 462         { CSU_CSLX_GPIO3, CSU_ALL_RW },
 463         { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
 464         { CSU_CSLX_CSU, CSU_ALL_RW },
 465         { CSU_CSLX_ASRC, CSU_ALL_RW },
 466         { CSU_CSLX_SPDIF, CSU_ALL_RW },
 467         { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
 468         { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
 469         { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
 470         { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
 471         { CSU_CSLX_SAI2, CSU_ALL_RW },
 472         { CSU_CSLX_SAI1, CSU_ALL_RW },
 473         { CSU_CSLX_SAI4, CSU_ALL_RW },
 474         { CSU_CSLX_SAI3, CSU_ALL_RW },
 475         { CSU_CSLX_FTM2, CSU_ALL_RW },
 476         { CSU_CSLX_FTM1, CSU_ALL_RW },
 477         { CSU_CSLX_FTM4, CSU_ALL_RW },
 478         { CSU_CSLX_FTM3, CSU_ALL_RW },
 479         { CSU_CSLX_FTM6, CSU_ALL_RW },
 480         { CSU_CSLX_FTM5, CSU_ALL_RW },
 481         { CSU_CSLX_FTM8, CSU_ALL_RW },
 482         { CSU_CSLX_FTM7, CSU_ALL_RW },
 483         { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
 484         { CSU_CSLX_EPU, CSU_ALL_RW },
 485         { CSU_CSLX_GDI, CSU_ALL_RW },
 486         { CSU_CSLX_DDI, CSU_ALL_RW },
 487         { CSU_CSLX_RESERVED1, CSU_ALL_RW },
 488         { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
 489         { CSU_CSLX_RESERVED2, CSU_ALL_RW },
 490 };
 491 #endif
 492
 493 struct liodn_id_table sec_liodn_tbl[] = {
 494         SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
 495         SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
 496         SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
 497         SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
 498         SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
 499         SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
 500         SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
 501         SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
 502         SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
 503         SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
 504         SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
 505         SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
 506         SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
 507         SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
 508         SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
 509         SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
 510 };
 511
 512 struct smmu_stream_id dev_stream_id[] = {
 513         { 0x100, 0x01, "ETSEC MAC1" },
 514         { 0x104, 0x02, "ETSEC MAC2" },
 515         { 0x108, 0x03, "ETSEC MAC3" },
 516         { 0x10c, 0x04, "PEX1" },
 517         { 0x110, 0x05, "PEX2" },
 518         { 0x114, 0x06, "qDMA" },
 519         { 0x118, 0x07, "SATA" },
 520         { 0x11c, 0x08, "USB3" },
 521         { 0x120, 0x09, "QE" },
 522         { 0x124, 0x0a, "eSDHC" },
 523         { 0x128, 0x0b, "eMA" },
 524         { 0x14c, 0x0c, "2D-ACE" },
 525         { 0x150, 0x0d, "USB2" },
 526         { 0x18c, 0x0e, "DEBUG" },
 527 };
 528
 529 int board_init(void)
 530 {
 531 #ifndef CONFIG_SYS_FSL_NO_SERDES
 532         fsl_serdes_init();
 533 #ifndef CONFIG_QSPI_BOOT
 534         config_serdes_mux();
 535 #endif
 536 #endif
 537
 538         ls1021x_config_caam_stream_id(sec_liodn_tbl,
 539                                       ARRAY_SIZE(sec_liodn_tbl));
 540         ls102xa_config_smmu_stream_id(dev_stream_id,
 541                                       ARRAY_SIZE(dev_stream_id));
 542
 543 #ifdef CONFIG_LS102XA_NS_ACCESS
 544         enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 545 #endif
 546
 547 #ifdef CONFIG_U_QE
 548         u_qe_init();
 549 #endif
 550
 551         return 0;
 552 }
 553
 554 #if defined(CONFIG_MISC_INIT_R)
 555 int misc_init_r(void)
 556 {
 557 #ifndef CONFIG_QSPI_BOOT
 558         config_board_mux();
 559 #endif
 560
 561 #ifdef CONFIG_FSL_CAAM
 562         return sec_init();
 563 #endif
 564 }
 565 #endif
 566
 567 int ft_board_setup(void *blob, bd_t *bd)
 568 {
 569         ft_cpu_setup(blob, bd);
 570
 571 #ifdef CONFIG_PCIE_LAYERSCAPE
 572         ft_pcie_setup(blob, bd);
 573 #endif
 574
 575         return 0;
 576 }
 577
 578 u8 flash_read8(void *addr)
 579 {
 580         return __raw_readb(addr + 1);
 581 }
 582
 583 void flash_write16(u16 val, void *addr)
 584 {
 585         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 586
 587         __raw_writew(shftval, addr);
 588 }
 589
 590 u16 flash_read16(void *addr)
 591 {
 592         u16 val = __raw_readw(addr);
 593
 594         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 595 }
 596
 597 #ifndef CONFIG_QSPI_BOOT
 598 static void convert_flash_bank(char bank)
 599 {
 600         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 601
 602         printf("Now switch to boot from flash bank %d.\n", bank);
 603         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 604         cpld_data->vbank = bank;
 605
 606         printf("Reset board to enable configuration.\n");
 607         cpld_data->system_rst = CONFIG_RESET;
 608 }
 609
 610 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 611                           char * const argv[])
 612 {
 613         if (argc != 2)
 614                 return CMD_RET_USAGE;
 615         if (strcmp(argv[1], "0") == 0)
 616                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 617         else if (strcmp(argv[1], "1") == 0)
 618                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 619         else
 620                 return CMD_RET_USAGE;
 621
 622         return 0;
 623 }
 624
 625 U_BOOT_CMD(
 626         boot_bank, 2, 0, flash_bank_cmd,
 627         "Flash bank Selection Control",
 628         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 629 );
 630
 631 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 632                           char * const argv[])
 633 {
 634         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 635
 636         if (argc > 2)
 637                 return CMD_RET_USAGE;
 638         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 639                 cpld_data->system_rst = CONFIG_RESET;
 640         else if (strcmp(argv[1], "init") == 0)
 641                 cpld_data->global_rst = INIT_RESET;
 642         else
 643                 return CMD_RET_USAGE;
 644
 645         return 0;
 646 }
 647
 648 U_BOOT_CMD(
 649         cpld_reset, 2, 0, cpld_reset_cmd,
 650         "Reset via CPLD",
 651         "conf\n"
 652         "       -reset with current CPLD configuration\n"
 653         "init\n"
 654         "       -reset and initial CPLD configuration with default value"
 655
 656 );
 657
 658 static void convert_serdes_mux(int type, int need_reset)
 659 {
 660         char current_serdes;
 661         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 662
 663         current_serdes = cpld_data->serdes_mux;
 664
 665         switch (type) {
 666         case LANEB_SATA:
 667                 current_serdes &= ~MASK_LANE_B;
 668                 break;
 669         case LANEB_SGMII1:
 670                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 671                 break;
 672         case LANEC_SGMII1:
 673                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 674                 break;
 675         case LANED_SGMII2:
 676                 current_serdes |= MASK_LANE_D;
 677                 break;
 678         case LANEC_PCIEX1:
 679                 current_serdes |= MASK_LANE_C;
 680                 break;
 681         case (LANED_PCIEX2 | LANEC_PCIEX1):
 682                 current_serdes |= MASK_LANE_C;
 683                 current_serdes &= ~MASK_LANE_D;
 684                 break;
 685         default:
 686                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 687                 return;
 688         }
 689
 690         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 691         cpld_data->serdes_mux = current_serdes;
 692
 693         if (need_reset == 1) {
 694                 printf("Reset board to enable configuration\n");
 695                 cpld_data->system_rst = CONFIG_RESET;
 696         }
 697 }
 698
 699 void print_serdes_mux(void)
 700 {
 701         char current_serdes;
 702         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 703
 704         current_serdes = cpld_data->serdes_mux;
 705
 706         printf("Serdes Lane B: ");
 707         if ((current_serdes & MASK_LANE_B) == 0)
 708                 printf("SATA,\n");
 709         else
 710                 printf("SGMII 1,\n");
 711
 712         printf("Serdes Lane C: ");
 713         if ((current_serdes & MASK_LANE_C) == 0)
 714                 printf("SGMII 1,\n");
 715         else
 716                 printf("PCIe,\n");
 717
 718         printf("Serdes Lane D: ");
 719         if ((current_serdes & MASK_LANE_D) == 0)
 720                 printf("PCIe,\n");
 721         else
 722                 printf("SGMII 2,\n");
 723
 724         printf("SGMII 1 is on lane ");
 725         if ((current_serdes & MASK_SGMII) == 0)
 726                 printf("C.\n");
 727         else
 728                 printf("B.\n");
 729 }
 730
 731 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 732                           char * const argv[])
 733 {
 734         if (argc != 2)
 735                 return CMD_RET_USAGE;
 736         if (strcmp(argv[1], "sata") == 0) {
 737                 printf("Set serdes lane B to SATA.\n");
 738                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 739         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 740                 printf("Set serdes lane B to SGMII 1.\n");
 741                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 742         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 743                 printf("Set serdes lane C to SGMII 1.\n");
 744                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 745         } else if (strcmp(argv[1], "sgmii2") == 0) {
 746                 printf("Set serdes lane D to SGMII 2.\n");
 747                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 748         } else if (strcmp(argv[1], "pciex1") == 0) {
 749                 printf("Set serdes lane C to PCIe X1.\n");
 750                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 751         } else if (strcmp(argv[1], "pciex2") == 0) {
 752                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 753                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 754         } else if (strcmp(argv[1], "show") == 0) {
 755                 print_serdes_mux();
 756         } else {
 757                 return CMD_RET_USAGE;
 758         }
 759
 760         return 0;
 761 }
 762
 763 U_BOOT_CMD(
 764         lane_bank, 2, 0, serdes_mux_cmd,
 765         "Multiplexed function setting for SerDes Lanes",
 766         "sata\n"
 767         "       -change lane B to sata\n"
 768         "lane_bank sgmii1b\n"
 769         "       -change lane B to SGMII1\n"
 770         "lane_bank sgmii1c\n"
 771         "       -change lane C to SGMII1\n"
 772         "lane_bank sgmii2\n"
 773         "       -change lane D to SGMII2\n"
 774         "lane_bank pciex1\n"
 775         "       -change lane C to PCIeX1\n"
 776         "lane_bank pciex2\n"
 777         "       -change lane C & lane D to PCIeX2\n"
 778         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 779 );
 780 #endif