2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/immap_ls102xa.h>
11 #include <asm/arch/ns_access.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/ls102xa_stream_id.h>
17 #include <fsl_esdhc.h>
25 #include "../../../drivers/qe/qe.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 #define VERSION_MASK 0x00FF
32 #define BANK_MASK 0x0001
33 #define CONFIG_RESET 0x1
34 #define INIT_RESET 0x1
36 #define CPLD_SET_MUX_SERDES 0x20
37 #define CPLD_SET_BOOT_BANK 0x40
39 #define BOOT_FROM_UPPER_BANK 0x0
40 #define BOOT_FROM_LOWER_BANK 0x1
42 #define LANEB_SATA (0x01)
43 #define LANEB_SGMII1 (0x02)
44 #define LANEC_SGMII1 (0x04)
45 #define LANEC_PCIEX1 (0x08)
46 #define LANED_PCIEX2 (0x10)
47 #define LANED_SGMII2 (0x20)
49 #define MASK_LANE_B 0x1
50 #define MASK_LANE_C 0x2
51 #define MASK_LANE_D 0x4
52 #define MASK_SGMII 0x8
54 #define KEEP_STATUS 0x0
55 #define NEED_RESET 0x1
57 #define SOFT_MUX_ON_I2C3_IFC 0x2
58 #define SOFT_MUX_ON_CAN3_USB2 0x8
59 #define SOFT_MUX_ON_QE_LCD 0x10
61 #define PIN_I2C3_IFC_MUX_I2C3 0x0
62 #define PIN_I2C3_IFC_MUX_IFC 0x1
63 #define PIN_CAN3_USB2_MUX_USB2 0x0
64 #define PIN_CAN3_USB2_MUX_CAN3 0x1
65 #define PIN_QE_LCD_MUX_LCD 0x0
66 #define PIN_QE_LCD_MUX_QE 0x1
69 u8 cpld_ver; /* cpld revision */
70 u8 cpld_ver_sub; /* cpld sub revision */
71 u8 pcba_ver; /* pcb revision number */
72 u8 system_rst; /* reset system by cpld */
73 u8 soft_mux_on; /* CPLD override physical switches Enable */
74 u8 cfg_rcw_src1; /* Reset config word 1 */
75 u8 cfg_rcw_src2; /* Reset config word 2 */
76 u8 vbank; /* Flash bank selection Control */
77 u8 gpio; /* GPIO for TWR-ELEV */
80 u8 can3_usb2_mux; /* CAN3 and USB2 Selection */
81 u8 qe_lcd_mux; /* QE and LCD Selection */
82 u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */
83 u8 global_rst; /* reset with init CPLD reg to default */
84 u8 rev1; /* Reserved */
85 u8 rev2; /* Reserved */
88 #ifndef CONFIG_QSPI_BOOT
89 static void convert_serdes_mux(int type, int need_reset);
93 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
95 printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n",
96 in_8(&cpld_data->cpld_ver) & VERSION_MASK,
97 in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
98 in_8(&cpld_data->pcba_ver) & VERSION_MASK,
99 in_8(&cpld_data->vbank) & BANK_MASK);
102 printf("soft_mux_on =%x\n",
103 in_8(&cpld_data->soft_mux_on));
104 printf("cfg_rcw_src1 =%x\n",
105 in_8(&cpld_data->cfg_rcw_src1));
106 printf("cfg_rcw_src2 =%x\n",
107 in_8(&cpld_data->cfg_rcw_src2));
108 printf("vbank =%x\n",
109 in_8(&cpld_data->vbank));
111 in_8(&cpld_data->gpio));
112 printf("i2c3_ifc_mux =%x\n",
113 in_8(&cpld_data->i2c3_ifc_mux));
114 printf("mux_spi2 =%x\n",
115 in_8(&cpld_data->mux_spi2));
116 printf("can3_usb2_mux =%x\n",
117 in_8(&cpld_data->can3_usb2_mux));
118 printf("qe_lcd_mux =%x\n",
119 in_8(&cpld_data->qe_lcd_mux));
120 printf("serdes_mux =%x\n",
121 in_8(&cpld_data->serdes_mux));
128 puts("Board: LS1021ATWR\n");
129 #ifndef CONFIG_QSPI_BOOT
136 unsigned int get_soc_major_rev(void)
138 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
139 unsigned int svr, major;
141 svr = in_be32(&gur->svr);
142 major = SVR_MAJ(svr);
147 void ddrmc_init(void)
149 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
151 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
153 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
154 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
156 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
157 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
158 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
159 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
160 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
161 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
163 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
165 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
166 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
168 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
170 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
172 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
173 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
175 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
176 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
178 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
179 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
181 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
183 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN);
188 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
192 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
196 #ifdef CONFIG_FSL_ESDHC
197 struct fsl_esdhc_cfg esdhc_cfg[1] = {
198 {CONFIG_SYS_FSL_ESDHC_ADDR},
201 int board_mmc_init(bd_t *bis)
203 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
205 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
209 #ifdef CONFIG_TSEC_ENET
210 int board_eth_init(bd_t *bis)
212 struct fsl_pq_mdio_info mdio_info;
213 struct tsec_info_struct tsec_info[4];
217 SET_STD_TSEC_INFO(tsec_info[num], 1);
218 if (is_serdes_configured(SGMII_TSEC1)) {
219 puts("eTSEC1 is in sgmii mode.\n");
220 tsec_info[num].flags |= TSEC_SGMII;
225 SET_STD_TSEC_INFO(tsec_info[num], 2);
226 if (is_serdes_configured(SGMII_TSEC2)) {
227 puts("eTSEC2 is in sgmii mode.\n");
228 tsec_info[num].flags |= TSEC_SGMII;
233 SET_STD_TSEC_INFO(tsec_info[num], 3);
237 printf("No TSECs initialized\n");
241 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
242 mdio_info.name = DEFAULT_MII_NAME;
243 fsl_pq_mdio_init(bis, &mdio_info);
245 tsec_eth_init(bis, tsec_info, num);
247 return pci_eth_init(bis);
251 #ifndef CONFIG_QSPI_BOOT
252 int config_serdes_mux(void)
254 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
255 u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
257 protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
260 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
261 convert_serdes_mux(LANED_PCIEX2 |
262 LANEC_PCIEX1, KEEP_STATUS);
265 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
266 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
267 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
270 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
271 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
272 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
275 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
276 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
277 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
285 #ifndef CONFIG_QSPI_BOOT
286 int config_board_mux(void)
288 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
292 if (hwconfig("i2c3")) {
294 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
295 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
298 if (hwconfig("ifc")) {
300 /* some signals can not enable simultaneous*/
301 if (conflict_flag > 1)
303 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
304 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
308 if (hwconfig("usb2")) {
310 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
311 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
314 if (hwconfig("can3")) {
316 /* some signals can not enable simultaneous*/
317 if (conflict_flag > 1)
319 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
320 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
324 if (hwconfig("lcd")) {
326 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
327 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
330 if (hwconfig("qe")) {
332 /* some signals can not enable simultaneous*/
333 if (conflict_flag > 1)
335 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
336 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
342 printf("WARNING: pin conflict! MUX setting may failed!\n");
347 int board_early_init_f(void)
349 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
350 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
353 #ifdef CONFIG_TSEC_ENET
354 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
355 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
358 #ifdef CONFIG_FSL_IFC
359 init_early_memctl_regs();
362 #ifdef CONFIG_FSL_DCU_FB
363 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
366 #ifdef CONFIG_FSL_QSPI
367 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
371 * Enable snoop requests and DVM message requests for
372 * Slave insterface S4 (A7 core cluster)
374 out_le32(&cci->slave[4].snoop_ctrl,
375 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
377 major = get_soc_major_rev();
378 if (major == SOC_MAJOR_VER_1_0) {
380 * Set CCI-400 Slave interface S1, S2 Shareable Override
381 * Register All transactions are treated as non-shareable
383 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
384 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
390 #ifdef CONFIG_SPL_BUILD
391 void board_init_f(ulong dummy)
394 memset(__bss_start, 0, __bss_end - __bss_start);
398 preloader_console_init();
402 board_init_r(NULL, 0);
406 #ifdef CONFIG_LS102XA_NS_ACCESS
407 static struct csu_ns_dev ns_dev[] = {
408 { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
409 { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
410 { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
411 { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
412 { CSU_CSLX_OCRAM, CSU_ALL_RW },
413 { CSU_CSLX_GIC, CSU_ALL_RW },
414 { CSU_CSLX_PCIE1, CSU_ALL_RW },
415 { CSU_CSLX_OCRAM2, CSU_ALL_RW },
416 { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
417 { CSU_CSLX_PCIE2, CSU_ALL_RW },
418 { CSU_CSLX_SATA, CSU_ALL_RW },
419 { CSU_CSLX_USB3, CSU_ALL_RW },
420 { CSU_CSLX_SERDES, CSU_ALL_RW },
421 { CSU_CSLX_QDMA, CSU_ALL_RW },
422 { CSU_CSLX_LPUART2, CSU_ALL_RW },
423 { CSU_CSLX_LPUART1, CSU_ALL_RW },
424 { CSU_CSLX_LPUART4, CSU_ALL_RW },
425 { CSU_CSLX_LPUART3, CSU_ALL_RW },
426 { CSU_CSLX_LPUART6, CSU_ALL_RW },
427 { CSU_CSLX_LPUART5, CSU_ALL_RW },
428 { CSU_CSLX_DSPI2, CSU_ALL_RW },
429 { CSU_CSLX_DSPI1, CSU_ALL_RW },
430 { CSU_CSLX_QSPI, CSU_ALL_RW },
431 { CSU_CSLX_ESDHC, CSU_ALL_RW },
432 { CSU_CSLX_2D_ACE, CSU_ALL_RW },
433 { CSU_CSLX_IFC, CSU_ALL_RW },
434 { CSU_CSLX_I2C1, CSU_ALL_RW },
435 { CSU_CSLX_USB2, CSU_ALL_RW },
436 { CSU_CSLX_I2C3, CSU_ALL_RW },
437 { CSU_CSLX_I2C2, CSU_ALL_RW },
438 { CSU_CSLX_DUART2, CSU_ALL_RW },
439 { CSU_CSLX_DUART1, CSU_ALL_RW },
440 { CSU_CSLX_WDT2, CSU_ALL_RW },
441 { CSU_CSLX_WDT1, CSU_ALL_RW },
442 { CSU_CSLX_EDMA, CSU_ALL_RW },
443 { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
444 { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
445 { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
446 { CSU_CSLX_DDR, CSU_ALL_RW },
447 { CSU_CSLX_QUICC, CSU_ALL_RW },
448 { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
449 { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
450 { CSU_CSLX_SFP, CSU_ALL_RW },
451 { CSU_CSLX_TMU, CSU_ALL_RW },
452 { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
453 { CSU_CSLX_RESERVED0, CSU_ALL_RW },
454 { CSU_CSLX_ETSEC1, CSU_ALL_RW },
455 { CSU_CSLX_SEC5_5, CSU_ALL_RW },
456 { CSU_CSLX_ETSEC3, CSU_ALL_RW },
457 { CSU_CSLX_ETSEC2, CSU_ALL_RW },
458 { CSU_CSLX_GPIO2, CSU_ALL_RW },
459 { CSU_CSLX_GPIO1, CSU_ALL_RW },
460 { CSU_CSLX_GPIO4, CSU_ALL_RW },
461 { CSU_CSLX_GPIO3, CSU_ALL_RW },
462 { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
463 { CSU_CSLX_CSU, CSU_ALL_RW },
464 { CSU_CSLX_ASRC, CSU_ALL_RW },
465 { CSU_CSLX_SPDIF, CSU_ALL_RW },
466 { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
467 { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
468 { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
469 { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
470 { CSU_CSLX_SAI2, CSU_ALL_RW },
471 { CSU_CSLX_SAI1, CSU_ALL_RW },
472 { CSU_CSLX_SAI4, CSU_ALL_RW },
473 { CSU_CSLX_SAI3, CSU_ALL_RW },
474 { CSU_CSLX_FTM2, CSU_ALL_RW },
475 { CSU_CSLX_FTM1, CSU_ALL_RW },
476 { CSU_CSLX_FTM4, CSU_ALL_RW },
477 { CSU_CSLX_FTM3, CSU_ALL_RW },
478 { CSU_CSLX_FTM6, CSU_ALL_RW },
479 { CSU_CSLX_FTM5, CSU_ALL_RW },
480 { CSU_CSLX_FTM8, CSU_ALL_RW },
481 { CSU_CSLX_FTM7, CSU_ALL_RW },
482 { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
483 { CSU_CSLX_EPU, CSU_ALL_RW },
484 { CSU_CSLX_GDI, CSU_ALL_RW },
485 { CSU_CSLX_DDI, CSU_ALL_RW },
486 { CSU_CSLX_RESERVED1, CSU_ALL_RW },
487 { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
488 { CSU_CSLX_RESERVED2, CSU_ALL_RW },
492 struct liodn_id_table sec_liodn_tbl[] = {
493 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
494 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
495 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
496 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
497 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
498 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
499 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
500 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
501 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
502 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
503 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
504 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
505 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
506 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
507 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
508 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
511 struct smmu_stream_id dev_stream_id[] = {
512 { 0x100, 0x01, "ETSEC MAC1" },
513 { 0x104, 0x02, "ETSEC MAC2" },
514 { 0x108, 0x03, "ETSEC MAC3" },
515 { 0x10c, 0x04, "PEX1" },
516 { 0x110, 0x05, "PEX2" },
517 { 0x114, 0x06, "qDMA" },
518 { 0x118, 0x07, "SATA" },
519 { 0x11c, 0x08, "USB3" },
520 { 0x120, 0x09, "QE" },
521 { 0x124, 0x0a, "eSDHC" },
522 { 0x128, 0x0b, "eMA" },
523 { 0x14c, 0x0c, "2D-ACE" },
524 { 0x150, 0x0d, "USB2" },
525 { 0x18c, 0x0e, "DEBUG" },
530 #ifndef CONFIG_SYS_FSL_NO_SERDES
532 #ifndef CONFIG_QSPI_BOOT
537 ls1021x_config_caam_stream_id(sec_liodn_tbl,
538 ARRAY_SIZE(sec_liodn_tbl));
539 ls102xa_config_smmu_stream_id(dev_stream_id,
540 ARRAY_SIZE(dev_stream_id));
542 #ifdef CONFIG_LS102XA_NS_ACCESS
543 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
553 #if defined(CONFIG_MISC_INIT_R)
554 int misc_init_r(void)
556 #ifndef CONFIG_QSPI_BOOT
560 #ifdef CONFIG_FSL_CAAM
566 int ft_board_setup(void *blob, bd_t *bd)
568 ft_cpu_setup(blob, bd);
571 ft_pci_setup(blob, bd);
577 u8 flash_read8(void *addr)
579 return __raw_readb(addr + 1);
582 void flash_write16(u16 val, void *addr)
584 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
586 __raw_writew(shftval, addr);
589 u16 flash_read16(void *addr)
591 u16 val = __raw_readw(addr);
593 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
596 #ifndef CONFIG_QSPI_BOOT
597 static void convert_flash_bank(char bank)
599 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
601 printf("Now switch to boot from flash bank %d.\n", bank);
602 cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
603 cpld_data->vbank = bank;
605 printf("Reset board to enable configuration.\n");
606 cpld_data->system_rst = CONFIG_RESET;
609 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
613 return CMD_RET_USAGE;
614 if (strcmp(argv[1], "0") == 0)
615 convert_flash_bank(BOOT_FROM_UPPER_BANK);
616 else if (strcmp(argv[1], "1") == 0)
617 convert_flash_bank(BOOT_FROM_LOWER_BANK);
619 return CMD_RET_USAGE;
625 boot_bank, 2, 0, flash_bank_cmd,
626 "Flash bank Selection Control",
627 "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
630 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
633 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
636 return CMD_RET_USAGE;
637 if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
638 cpld_data->system_rst = CONFIG_RESET;
639 else if (strcmp(argv[1], "init") == 0)
640 cpld_data->global_rst = INIT_RESET;
642 return CMD_RET_USAGE;
648 cpld_reset, 2, 0, cpld_reset_cmd,
651 " -reset with current CPLD configuration\n"
653 " -reset and initial CPLD configuration with default value"
657 static void convert_serdes_mux(int type, int need_reset)
660 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
662 current_serdes = cpld_data->serdes_mux;
666 current_serdes &= ~MASK_LANE_B;
669 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
672 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
675 current_serdes |= MASK_LANE_D;
678 current_serdes |= MASK_LANE_C;
680 case (LANED_PCIEX2 | LANEC_PCIEX1):
681 current_serdes |= MASK_LANE_C;
682 current_serdes &= ~MASK_LANE_D;
685 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
689 cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
690 cpld_data->serdes_mux = current_serdes;
692 if (need_reset == 1) {
693 printf("Reset board to enable configuration\n");
694 cpld_data->system_rst = CONFIG_RESET;
698 void print_serdes_mux(void)
701 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
703 current_serdes = cpld_data->serdes_mux;
705 printf("Serdes Lane B: ");
706 if ((current_serdes & MASK_LANE_B) == 0)
709 printf("SGMII 1,\n");
711 printf("Serdes Lane C: ");
712 if ((current_serdes & MASK_LANE_C) == 0)
713 printf("SGMII 1,\n");
717 printf("Serdes Lane D: ");
718 if ((current_serdes & MASK_LANE_D) == 0)
721 printf("SGMII 2,\n");
723 printf("SGMII 1 is on lane ");
724 if ((current_serdes & MASK_SGMII) == 0)
730 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
734 return CMD_RET_USAGE;
735 if (strcmp(argv[1], "sata") == 0) {
736 printf("Set serdes lane B to SATA.\n");
737 convert_serdes_mux(LANEB_SATA, NEED_RESET);
738 } else if (strcmp(argv[1], "sgmii1b") == 0) {
739 printf("Set serdes lane B to SGMII 1.\n");
740 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
741 } else if (strcmp(argv[1], "sgmii1c") == 0) {
742 printf("Set serdes lane C to SGMII 1.\n");
743 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
744 } else if (strcmp(argv[1], "sgmii2") == 0) {
745 printf("Set serdes lane D to SGMII 2.\n");
746 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
747 } else if (strcmp(argv[1], "pciex1") == 0) {
748 printf("Set serdes lane C to PCIe X1.\n");
749 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
750 } else if (strcmp(argv[1], "pciex2") == 0) {
751 printf("Set serdes lane C & lane D to PCIe X2.\n");
752 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
753 } else if (strcmp(argv[1], "show") == 0) {
756 return CMD_RET_USAGE;
763 lane_bank, 2, 0, serdes_mux_cmd,
764 "Multiplexed function setting for SerDes Lanes",
766 " -change lane B to sata\n"
767 "lane_bank sgmii1b\n"
768 " -change lane B to SGMII1\n"
769 "lane_bank sgmii1c\n"
770 " -change lane C to SGMII1\n"
772 " -change lane D to SGMII2\n"
774 " -change lane C to PCIeX1\n"
776 " -change lane C & lane D to PCIeX2\n"
777 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"