2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
16 #include <fsl_debug_server.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
20 #include <asm/arch-fsl-lsch3/soc.h>
22 #include "../common/qixis.h"
23 #include "ls2085ardb_qixis.h"
25 #define PIN_MUX_SEL_SDHC 0x00
27 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
28 DECLARE_GLOBAL_DATA_PTR;
34 unsigned long long get_qixis_addr(void)
36 unsigned long long addr;
38 if (gd->flags & GD_FLG_RELOC)
39 addr = QIXIS_BASE_PHYS;
41 addr = QIXIS_BASE_PHYS_EARLY;
44 * IFC address under 256MB is mapped to 0x30000000, any address above
45 * is mapped to 0x5_10000000 up to 4GB.
47 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
58 printf("Board: %s-RDB, ", buf);
60 sw = QIXIS_READ(arch);
61 printf("Board Arch: V%d, ", sw >> 4);
62 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
64 sw = QIXIS_READ(brdcfg[0]);
65 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
68 printf("vBank: %d\n", sw);
72 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
74 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
76 puts("SERDES1 Reference : ");
77 printf("Clock1 = 156.25MHz ");
78 printf("Clock2 = 156.25MHz");
80 puts("\nSERDES2 Reference : ");
81 printf("Clock1 = 100MHz ");
82 printf("Clock2 = 100MHz\n");
87 unsigned long get_board_sys_clk(void)
89 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
91 switch (sysclk_conf & 0x0F) {
94 case QIXIS_SYSCLK_100:
96 case QIXIS_SYSCLK_125:
98 case QIXIS_SYSCLK_133:
100 case QIXIS_SYSCLK_150:
102 case QIXIS_SYSCLK_160:
104 case QIXIS_SYSCLK_166:
110 int select_i2c_ch_pca9547(u8 ch)
114 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
116 puts("PCA: failed to select proper channel\n");
125 init_final_memctl_regs();
127 #ifdef CONFIG_ENV_IS_NOWHERE
128 gd->env_addr = (ulong)&default_environment[0];
130 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
132 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
137 int board_early_init_f(void)
139 fsl_lsch3_early_init_f();
143 int config_board_mux(int ctrl_type)
147 reg5 = QIXIS_READ(brdcfg[5]);
151 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
154 printf("Wrong mux interface type\n");
158 QIXIS_WRITE(brdcfg[5], reg5);
163 int misc_init_r(void)
165 if (hwconfig("sdhc"))
166 config_board_mux(MUX_TYPE_SDHC);
171 void detail_board_ddr_info(void)
174 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
176 if (gd->bd->bi_dram[2].size) {
178 print_size(gd->bd->bi_dram[2].size, "");
179 print_ddr_info(CONFIG_DP_DDR_CTRL);
185 gd->ram_size = initdram(0);
190 #if defined(CONFIG_ARCH_MISC_INIT)
191 int arch_misc_init(void)
193 #ifdef CONFIG_FSL_DEBUG_SERVER
201 unsigned long get_dram_size_to_hide(void)
203 unsigned long dram_to_hide = 0;
205 /* Carve the Debug Server private DRAM block from the end of DRAM */
206 #ifdef CONFIG_FSL_DEBUG_SERVER
207 dram_to_hide += debug_server_get_dram_block_size();
210 /* Carve the MC private DRAM block from the end of DRAM */
211 #ifdef CONFIG_FSL_MC_ENET
212 dram_to_hide += mc_get_dram_block_size();
215 return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
218 #ifdef CONFIG_FSL_MC_ENET
219 void fdt_fixup_board_enet(void *fdt)
223 offset = fdt_path_offset(fdt, "/fsl-mc");
226 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
229 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
234 if (get_mc_boot_status() == 0)
235 fdt_status_okay(fdt, offset);
237 fdt_status_fail(fdt, offset);
241 #ifdef CONFIG_OF_BOARD_SETUP
242 int ft_board_setup(void *blob, bd_t *bd)
244 u64 base[CONFIG_NR_DRAM_BANKS];
245 u64 size[CONFIG_NR_DRAM_BANKS];
247 ft_cpu_setup(blob, bd);
249 /* fixup DT for the two GPP DDR banks */
250 base[0] = gd->bd->bi_dram[0].start;
251 size[0] = gd->bd->bi_dram[0].size;
252 base[1] = gd->bd->bi_dram[1].start;
253 size[1] = gd->bd->bi_dram[1].size;
255 fdt_fixup_memory_banks(blob, base, size, 2);
257 #ifdef CONFIG_FSL_MC_ENET
258 fdt_fixup_board_enet(blob);
259 fsl_mc_ldpaa_exit(bd);
266 void qixis_dump_switch(void)
270 QIXIS_WRITE(cms[0], 0x00);
271 nr_of_cfgsw = QIXIS_READ(cms[1]);
273 puts("DIP switch settings dump:\n");
274 for (i = 1; i <= nr_of_cfgsw; i++) {
275 QIXIS_WRITE(cms[0], i);
276 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
281 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
282 * Both slots has 0x54, resulting 2nd slot unusable.
284 void update_spd_address(unsigned int ctrl_num,
290 sw = QIXIS_READ(arch);
291 if ((sw & 0xf) < 0x3) {
292 if (ctrl_num == 1 && slot == 0)
293 *addr = SPD_EEPROM_ADDRESS4;
294 else if (ctrl_num == 1 && slot == 1)
295 *addr = SPD_EEPROM_ADDRESS3;