2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
7 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/immap.h>
32 #define PERIOD 13 /* system bus period in ns */
33 #define SDRAM_TREFI 7800 /* in ns */
38 puts("Freescale MCF5275 EVB\n");
42 phys_size_t initdram(int board_type)
44 sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
45 gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
48 out_be16(&gpio_reg->par_sdram, 0x3FF);
50 /* Set up chip select */
51 out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
52 out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
55 out_be32(&sdp->sdcfg1, 0x83711630);
56 out_be32(&sdp->sdcfg2, 0x46770000);
59 out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
62 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
64 /* Dummy write to start SDRAM */
65 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
68 setbits_be32(&sdp->sdmr,
69 MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
71 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
74 out_be32(&sdp->sdmr, 0x058d0000);
75 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
77 /* Stop sending commands */
78 clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
81 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
82 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
84 /* Stop manual precharge, send 2 IREF */
85 clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
86 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
87 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
88 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
91 out_be32(&sdp->sdmr, 0x018d0000);
92 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
94 /* Stop sending commands */
95 clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
96 clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
98 /* Turn on auto refresh, lock SDMR */
101 | MCF_SDRAMC_SDCR_REF
102 | MCF_SDRAMC_SDCR_MUX(1)
103 /* 1 added to round up */
104 | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
105 | MCF_SDRAMC_SDCR_DQS_OE(0x3));
107 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
112 /* TODO: XXX XXX XXX */
113 printf("DRAM test not implemented!\n");