2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/mpc8349_pci.h>
32 #include <spd_sdram.h>
34 #if defined(CONFIG_OF_LIBFDT)
38 #ifndef CONFIG_SPD_EEPROM
39 /*************************************************************************
40 * fixed sdram init -- doesn't use serial presence detect.
41 ************************************************************************/
44 volatile immap_t *im = (immap_t *) CFG_IMMR;
45 u32 ddr_size; /* The size of RAM, in bytes */
46 u32 ddr_size_log2 = 0;
48 for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
55 im->sysconf.ddrlaw[0].ar =
56 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
57 im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff;
59 /* Only one CS0 for DDR */
60 im->ddr.csbnds[0].csbnds = 0x0000000f;
61 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
63 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
64 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
66 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
67 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
69 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
70 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
71 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
73 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
74 im->ddr.sdram_interval =
75 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
76 SDRAM_INTERVAL_BSTOPRE_SHIFT);
77 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
81 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
83 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
84 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
85 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
86 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
87 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
95 * Initialize PCI Devices, report devices found
97 #ifndef CONFIG_PCI_PNP
98 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
106 pci_cfgfunc_config_device,
110 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
116 volatile static struct pci_controller hose[] = {
118 #ifndef CONFIG_PCI_PNP
119 config_table:pci_mpc83xxmitx_config_table,
123 #ifndef CONFIG_PCI_PNP
124 config_table:pci_mpc83xxmitx_config_table,
128 #endif /* CONFIG_PCI */
130 long int initdram(int board_type)
132 volatile immap_t *im = (immap_t *) CFG_IMMR;
134 #ifdef CONFIG_DDR_ECC
135 volatile ddr83xx_t *ddr = &im->ddr;
138 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
141 /* DDR SDRAM - Main SODIMM */
142 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
143 #ifdef CONFIG_SPD_EEPROM
146 msize = fixed_sdram();
149 #ifdef CONFIG_DDR_ECC
150 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
151 /* Unlike every other board, on the 83xx spd_sdram() returns
152 megabytes instead of just bytes. That's why we need to
153 multiple by 1MB when calling ddr_enable_ecc(). */
154 ddr_enable_ecc(msize * 1048576);
157 /* return total bus RAM size(bytes) */
158 return msize * 1024 * 1024;
163 #ifdef CONFIG_MPC8349ITX
164 puts("Board: Freescale MPC8349E-mITX\n");
166 puts("Board: Freescale MPC8349E-mITX-GP\n");
173 * Implement a work-around for a hardware problem with compact
176 * Program the UPM if compact flash is enabled.
178 int misc_init_f(void)
180 #ifdef CONFIG_VSC7385
181 volatile u32 *vsc7385_cpuctrl;
183 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
184 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
185 means it is 0 when the IRQ is not active. This makes the wire-AND
186 logic always assert IRQ7 to CPU even if there is no request from the
187 switch. Since the compact flash and the switch share the same IRQ,
188 the Linux kernel will think that the compact flash is requesting irq
189 and get stuck when it tries to clear the IRQ. Thus we need to set
190 the L2_IRQ0 and L2_IRQ1 to active low.
192 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
193 Without this code, compact flash will not work in Linux because
194 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
195 don't enable compact flash for U-Boot.
198 vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0);
199 *vsc7385_cpuctrl |= 0x0c;
202 #ifdef CONFIG_COMPACT_FLASH
203 /* UPM Table Configuration Code */
204 static uint UPMATable[] = {
205 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
206 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
207 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
210 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
211 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
212 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
213 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
216 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
217 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
218 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
219 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
220 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
222 volatile immap_t *immap = (immap_t *) CFG_IMMR;
223 volatile lbus83xx_t *lbus = &immap->lbus;
225 lbus->bank[3].br = CFG_BR3_PRELIM;
226 lbus->bank[3].or = CFG_OR3_PRELIM;
228 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
229 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
231 lbus->mamr = 0x08404440;
233 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
235 puts("UPMA: Configured for compact flash\n");
242 * Make sure the EEPROM has the HRCW correctly programmed.
243 * Make sure the RTC is correctly programmed.
245 * The MPC8349E-mITX can be configured to load the HRCW from
246 * EEPROM instead of flash. This is controlled via jumpers
247 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
248 * jumpered), but if they're set to 001 or 010, then the HRCW is
249 * read from the "I2C EEPROM".
251 * This function makes sure that the I2C EEPROM is programmed
254 int misc_init_r(void)
258 #ifdef CONFIG_HARD_I2C
260 unsigned int orig_bus = i2c_get_bus_num();
263 #ifdef CFG_I2C_RTC_ADDR
267 #ifdef CFG_I2C_EEPROM_ADDR
268 static u8 eeprom_data[] = /* HRCW data */
270 0xAA, 0x55, 0xAA, /* Preamble */
271 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
272 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
273 (CFG_HRCW_LOW >> 24) & 0xFF,
274 (CFG_HRCW_LOW >> 16) & 0xFF,
275 (CFG_HRCW_LOW >> 8) & 0xFF,
277 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
278 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
279 (CFG_HRCW_HIGH >> 24) & 0xFF,
280 (CFG_HRCW_HIGH >> 16) & 0xFF,
281 (CFG_HRCW_HIGH >> 8) & 0xFF,
285 u8 data[sizeof(eeprom_data)];
288 printf("Board revision: ");
290 if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
291 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
292 else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
293 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
299 #ifdef CFG_I2C_EEPROM_ADDR
302 if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
303 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
305 (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
306 sizeof(eeprom_data)) != 0) {
307 puts("Failure writing the HRCW to EEPROM via I2C.\n");
312 puts("Failure reading the HRCW from EEPROM via I2C.\n");
317 #ifdef CFG_I2C_RTC_ADDR
320 if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
323 /* Work-around for MPC8349E-mITX bug #13601.
324 If the RTC does not contain valid register values, the DS1339
325 Linux driver will not work.
328 /* Make sure status register bits 6-2 are zero */
329 ds1339_data[0x0f] &= ~0x7c;
331 /* Check for a valid day register value */
332 ds1339_data[0x03] &= ~0xf8;
333 if (ds1339_data[0x03] == 0) {
334 ds1339_data[0x03] = 1;
337 /* Check for a valid date register value */
338 ds1339_data[0x04] &= ~0xc0;
339 if ((ds1339_data[0x04] == 0) ||
340 ((ds1339_data[0x04] & 0x0f) > 9) ||
341 (ds1339_data[0x04] >= 0x32)) {
342 ds1339_data[0x04] = 1;
345 /* Check for a valid month register value */
346 ds1339_data[0x05] &= ~0x60;
348 if ((ds1339_data[0x05] == 0) ||
349 ((ds1339_data[0x05] & 0x0f) > 9) ||
350 ((ds1339_data[0x05] >= 0x13)
351 && (ds1339_data[0x05] <= 0x19))) {
352 ds1339_data[0x05] = 1;
355 /* Enable Oscillator and rate select */
356 ds1339_data[0x0e] = 0x1c;
358 /* Work-around for MPC8349E-mITX bug #13330.
359 Ensure that the RTC control register contains the value 0x1c.
360 This affects SATA performance.
364 (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data,
365 sizeof(ds1339_data))) {
366 puts("Failure writing to the RTC via I2C.\n");
370 puts("Failure reading from the RTC via I2C.\n");
375 i2c_set_bus_num(orig_bus);
381 #if defined(CONFIG_OF_BOARD_SETUP)
382 void ft_board_setup(void *blob, bd_t *bd)
384 ft_cpu_setup(blob, bd);
386 ft_pci_setup(blob, bd);