2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * CREDITS: Kim Phillips contribute to LIBFDT code
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
16 #if defined(CONFIG_SPD_EEPROM)
17 #include <spd_sdram.h>
19 #if defined(CONFIG_OF_LIBFDT)
22 #if defined(CONFIG_PQ_MDS_PIB)
23 #include "../common/pq-mds-pib.h"
26 int board_early_init_f(void)
28 u8 *bcsr = (u8 *)CFG_BCSR;
30 /* Enable flash write */
32 /* Clear all of the interrupt of BCSR */
38 int board_early_init_r(void)
40 #ifdef CONFIG_PQ_MDS_PIB
46 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
47 extern void ddr_enable_ecc(unsigned int dram_size);
49 int fixed_sdram(void);
51 long int initdram(int board_type)
53 volatile immap_t *im = (immap_t *) CFG_IMMR;
56 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
59 #if defined(CONFIG_SPD_EEPROM)
62 msize = fixed_sdram();
65 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
66 /* Initialize DDR ECC byte */
67 ddr_enable_ecc(msize * 1024 * 1024);
70 /* return total bus DDR size(bytes) */
71 return (msize * 1024 * 1024);
74 #if !defined(CONFIG_SPD_EEPROM)
75 /*************************************************************************
76 * fixed sdram init -- doesn't use serial presence detect.
77 ************************************************************************/
80 volatile immap_t *im = (immap_t *) CFG_IMMR;
81 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
82 u32 msize_log2 = __ilog2(msize);
84 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
85 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
87 #if (CFG_DDR_SIZE != 512)
88 #warning Currenly any ddr size other than 512 is not supported
90 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
93 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
96 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
97 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
100 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
101 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
102 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
103 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
104 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
105 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
106 im->ddr.sdram_mode = CFG_DDR_MODE;
107 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
108 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
109 __asm__ __volatile__("sync");
112 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
116 #endif /*!CFG_SPD_EEPROM */
120 puts("Board: Freescale MPC837xEMDS\n");
124 #if defined(CONFIG_OF_BOARD_SETUP)
125 void ft_board_setup(void *blob, bd_t *bd)
127 ft_cpu_setup(blob, bd);
129 ft_pci_setup(blob, bd);
132 #endif /* CONFIG_OF_BOARD_SETUP */