2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
18 #include <spd_sdram.h>
22 #if defined(CFG_DRAM_TEST)
26 uint *pstart = (uint *) CFG_MEMTEST_START;
27 uint *pend = (uint *) CFG_MEMTEST_END;
30 printf("Testing DRAM from 0x%08x to 0x%08x\n",
34 printf("DRAM test phase 1:\n");
35 for (p = pstart; p < pend; p++)
38 for (p = pstart; p < pend; p++) {
39 if (*p != 0xaaaaaaaa) {
40 printf("DRAM test fails at: %08x\n", (uint) p);
45 printf("DRAM test phase 2:\n");
46 for (p = pstart; p < pend; p++)
49 for (p = pstart; p < pend; p++) {
50 if (*p != 0x55555555) {
51 printf("DRAM test fails at: %08x\n", (uint) p);
56 printf("DRAM test passed.\n");
61 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
62 void ddr_enable_ecc(unsigned int dram_size);
64 int fixed_sdram(void);
66 long int initdram(int board_type)
68 immap_t *im = (immap_t *) CFG_IMMR;
71 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
74 #if defined(CONFIG_SPD_EEPROM)
77 msize = fixed_sdram();
80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
81 /* Initialize DDR ECC byte */
82 ddr_enable_ecc(msize * 1024 * 1024);
84 /* return total bus DDR size(bytes) */
85 return (msize * 1024 * 1024);
88 #if !defined(CONFIG_SPD_EEPROM)
89 /*************************************************************************
90 * fixed sdram init -- doesn't use serial presence detect.
91 ************************************************************************/
94 immap_t *im = (immap_t *) CFG_IMMR;
95 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
96 u32 msize_log2 = __ilog2(msize);
98 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
99 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
101 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
104 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
107 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
108 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
111 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
112 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
113 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
114 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
115 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
116 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
117 im->ddr.sdram_mode = CFG_DDR_MODE;
118 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
119 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
123 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
127 #endif /*!CFG_SPD_EEPROM */
131 puts("Board: Freescale MPC837xERDB\n");
136 * Miscellaneous late-boot configurations
138 * If a VSC7385 microcode image is present, then upload it.
140 int misc_init_r(void)
144 #ifdef CONFIG_VSC7385_IMAGE
145 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
146 CONFIG_VSC7385_IMAGE_SIZE)) {
147 puts("Failure uploading VSC7385 microcode.\n");
155 #if defined(CONFIG_OF_BOARD_SETUP)
157 void ft_board_setup(void *blob, bd_t *bd)
160 ft_pci_setup(blob, bd);
162 ft_cpu_setup(blob, bd);
164 #endif /* CONFIG_OF_BOARD_SETUP */