2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
36 #include <spd_sdram.h>
37 #include <fdt_support.h>
42 #include "../common/pixis.h"
43 #include "../common/sgmii_riser.h"
45 phys_size_t fixed_sdram(void);
49 printf ("Board: MPC8536DS, System ID: 0x%02x, "
50 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
51 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
52 in8(PIXIS_BASE + PIXIS_PVER));
57 initdram(int board_type)
59 phys_size_t dram_size = 0;
61 puts("Initializing....");
63 #ifdef CONFIG_SPD_EEPROM
64 dram_size = fsl_ddr_sdram();
66 dram_size = fixed_sdram();
68 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
69 dram_size *= 0x100000;
75 #if !defined(CONFIG_SPD_EEPROM)
77 * Fixed sdram init -- doesn't use serial presence detect.
80 phys_size_t fixed_sdram (void)
82 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
83 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
86 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
87 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
89 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
90 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
91 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
92 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
93 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
94 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
95 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
96 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
97 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
98 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
100 #if defined (CONFIG_DDR_ECC)
101 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
102 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
103 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
109 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
111 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
113 debug("DDR - 1st controller: memory initializing\n");
115 * Poll until memory is initialized.
116 * 512 Meg at 400 might hit this 200 times or so.
118 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
121 debug("DDR: memory initialized\n\n");
126 return 512 * 1024 * 1024;
132 static struct pci_controller pci1_hose;
136 static struct pci_controller pcie1_hose;
140 static struct pci_controller pcie2_hose;
144 static struct pci_controller pcie3_hose;
147 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
148 extern void fsl_pci_init(struct pci_controller *hose);
150 int first_free_busno=0;
155 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
156 uint devdisr = gur->devdisr;
158 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
159 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
160 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
162 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
163 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
165 if (sdrs2_io_sel == 7)
166 printf(" Serdes2 disalbed\n");
167 else if (sdrs2_io_sel == 4) {
168 printf(" eTSEC1 is in sgmii mode.\n");
169 printf(" eTSEC3 is in sgmii mode.\n");
170 } else if (sdrs2_io_sel == 6)
171 printf(" eTSEC1 is in sgmii mode.\n");
175 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
176 struct pci_controller *hose = &pcie3_hose;
177 int pcie_ep = (host_agent == 1);
178 int pcie_configured = (io_sel == 7);
179 struct pci_region *r = hose->regions;
181 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
182 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
183 pcie_ep ? "End Point" : "Root Complex",
185 if (pci->pme_msg_det) {
186 pci->pme_msg_det = 0xffffffff;
187 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
192 r += fsl_pci_setup_inbound_windows(r);
194 /* outbound memory */
196 CONFIG_SYS_PCIE3_MEM_BUS,
197 CONFIG_SYS_PCIE3_MEM_PHYS,
198 CONFIG_SYS_PCIE3_MEM_SIZE,
203 CONFIG_SYS_PCIE3_IO_BUS,
204 CONFIG_SYS_PCIE3_IO_PHYS,
205 CONFIG_SYS_PCIE3_IO_SIZE,
208 hose->region_count = r - hose->regions;
210 hose->first_busno=first_free_busno;
211 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
215 first_free_busno=hose->last_busno+1;
216 printf (" PCIE3 on bus %02x - %02x\n",
217 hose->first_busno,hose->last_busno);
219 printf (" PCIE3: disabled\n");
224 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
229 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
230 struct pci_controller *hose = &pcie1_hose;
231 int pcie_ep = (host_agent == 5);
232 int pcie_configured = (io_sel == 2 || io_sel == 3
233 || io_sel == 5 || io_sel == 7);
234 struct pci_region *r = hose->regions;
236 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
237 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
238 pcie_ep ? "End Point" : "Root Complex",
240 if (pci->pme_msg_det) {
241 pci->pme_msg_det = 0xffffffff;
242 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
247 r += fsl_pci_setup_inbound_windows(r);
249 /* outbound memory */
251 CONFIG_SYS_PCIE1_MEM_BUS,
252 CONFIG_SYS_PCIE1_MEM_PHYS,
253 CONFIG_SYS_PCIE1_MEM_SIZE,
258 CONFIG_SYS_PCIE1_IO_BUS,
259 CONFIG_SYS_PCIE1_IO_PHYS,
260 CONFIG_SYS_PCIE1_IO_SIZE,
263 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
264 /* outbound memory */
266 CONFIG_SYS_PCIE1_MEM_BUS2,
267 CONFIG_SYS_PCIE1_MEM_PHYS2,
268 CONFIG_SYS_PCIE1_MEM_SIZE2,
271 hose->region_count = r - hose->regions;
272 hose->first_busno=first_free_busno;
274 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
278 first_free_busno=hose->last_busno+1;
279 printf(" PCIE1 on bus %02x - %02x\n",
280 hose->first_busno,hose->last_busno);
283 printf (" PCIE1: disabled\n");
288 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
293 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
294 struct pci_controller *hose = &pcie2_hose;
295 int pcie_ep = (host_agent == 3);
296 int pcie_configured = (io_sel == 5 || io_sel == 7);
297 struct pci_region *r = hose->regions;
299 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
300 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
301 pcie_ep ? "End Point" : "Root Complex",
303 if (pci->pme_msg_det) {
304 pci->pme_msg_det = 0xffffffff;
305 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
310 r += fsl_pci_setup_inbound_windows(r);
312 /* outbound memory */
314 CONFIG_SYS_PCIE2_MEM_BUS,
315 CONFIG_SYS_PCIE2_MEM_PHYS,
316 CONFIG_SYS_PCIE2_MEM_SIZE,
321 CONFIG_SYS_PCIE2_IO_BUS,
322 CONFIG_SYS_PCIE2_IO_PHYS,
323 CONFIG_SYS_PCIE2_IO_SIZE,
326 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
327 /* outbound memory */
329 CONFIG_SYS_PCIE2_MEM_BUS2,
330 CONFIG_SYS_PCIE2_MEM_PHYS2,
331 CONFIG_SYS_PCIE2_MEM_SIZE2,
334 hose->region_count = r - hose->regions;
335 hose->first_busno=first_free_busno;
336 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
339 first_free_busno=hose->last_busno+1;
340 printf (" PCIE2 on bus %02x - %02x\n",
341 hose->first_busno,hose->last_busno);
344 printf (" PCIE2: disabled\n");
349 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
355 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
356 struct pci_controller *hose = &pci1_hose;
357 struct pci_region *r = hose->regions;
359 uint pci_agent = (host_agent == 6);
360 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
362 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
363 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
366 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
367 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
369 (pci_speed == 33333000) ? "33" :
370 (pci_speed == 66666000) ? "66" : "unknown",
371 pci_clk_sel ? "sync" : "async",
372 pci_agent ? "agent" : "host",
373 pci_arb ? "arbiter" : "external-arbiter",
378 r += fsl_pci_setup_inbound_windows(r);
380 /* outbound memory */
382 CONFIG_SYS_PCI1_MEM_BUS,
383 CONFIG_SYS_PCI1_MEM_PHYS,
384 CONFIG_SYS_PCI1_MEM_SIZE,
389 CONFIG_SYS_PCI1_IO_BUS,
390 CONFIG_SYS_PCI1_IO_PHYS,
391 CONFIG_SYS_PCI1_IO_SIZE,
394 #ifdef CONFIG_SYS_PCI1_MEM_BUS2
395 /* outbound memory */
397 CONFIG_SYS_PCI1_MEM_BUS2,
398 CONFIG_SYS_PCI1_MEM_PHYS2,
399 CONFIG_SYS_PCI1_MEM_SIZE2,
402 hose->region_count = r - hose->regions;
403 hose->first_busno=first_free_busno;
404 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
407 first_free_busno=hose->last_busno+1;
408 printf ("PCI on bus %02x - %02x\n",
409 hose->first_busno,hose->last_busno);
411 printf (" PCI: disabled\n");
415 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
420 int board_early_init_r(void)
422 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
423 const u8 flash_esel = 1;
426 * Remap Boot flash + PROMJET region to caching-inhibited
427 * so that flash can be erased properly.
430 /* Flush d-cache and invalidate i-cache of any FLASH data */
434 /* invalidate existing TLB entry for flash + promjet */
435 disable_tlb(flash_esel);
437 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
438 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
439 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
444 #ifdef CONFIG_GET_CLK_FROM_ICS307
445 /* decode S[0-2] to Output Divider (OD) */
448 10, 2, 8, 4, 5, 7, 3, 6
451 /* Calculate frequency being generated by ICS307-02 clock chip based upon
452 * the control bytes being programmed into it. */
453 /* XXX: This function should probably go into a common library */
455 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
457 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
458 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
459 unsigned long RDW = cw2 & 0x7F;
460 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
463 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
465 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
466 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
467 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
469 * R6:R0 = Reference Divider Word (RDW)
470 * V8:V0 = VCO Divider Word (VDW)
471 * S2:S0 = Output Divider Select (OD)
472 * F1:F0 = Function of CLK2 Output
474 * C1:C0 = internal load capacitance for cyrstal
477 /* Adding 1 to get a "nicely" rounded number, but this needs
478 * more tweaking to get a "properly" rounded number. */
480 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
482 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
488 get_board_sys_clk(ulong dummy)
490 return ics307_clk_freq (
491 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
492 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
493 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
498 get_board_ddr_clk(ulong dummy)
500 return ics307_clk_freq (
501 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
502 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
503 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
508 get_board_sys_clk(ulong dummy)
513 i = in8(PIXIS_BASE + PIXIS_SPD);
547 get_board_ddr_clk(ulong dummy)
552 i = in8(PIXIS_BASE + PIXIS_SPD);
586 int sata_initialize(void)
588 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
590 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
591 if (sdrs2_io_sel & 0x04)
594 return __sata_initialize();
597 int board_eth_init(bd_t *bis)
599 #ifdef CONFIG_TSEC_ENET
600 struct tsec_info_struct tsec_info[2];
601 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
604 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
607 SET_STD_TSEC_INFO(tsec_info[num], 1);
608 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
609 tsec_info[num].phyaddr = 0;
610 tsec_info[num].flags |= TSEC_SGMII;
615 SET_STD_TSEC_INFO(tsec_info[num], 3);
616 if (sdrs2_io_sel == 4) {
617 tsec_info[num].phyaddr = 1;
618 tsec_info[num].flags |= TSEC_SGMII;
624 printf("No TSECs initialized\n");
628 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
629 fsl_sgmii_riser_init(tsec_info, num);
631 tsec_eth_init(bis, tsec_info, num);
633 return pci_eth_init(bis);
636 #if defined(CONFIG_OF_BOARD_SETUP)
637 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
638 struct pci_controller *hose);
640 void ft_board_setup(void *blob, bd_t *bd)
642 ft_cpu_setup(blob, bd);
645 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
648 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
651 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
654 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);