2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
32 #include <spd_sdram.h>
34 #include <fdt_support.h>
36 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
37 extern void ddr_enable_ecc(unsigned int dram_size);
40 void local_bus_init(void);
41 void sdram_init(void);
42 long int fixed_sdram(void);
45 int board_early_init_f (void)
55 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
56 CONFIG_SYS_CLK_FREQ / 1000000);
58 printf(" PCI1: disabled\n");
62 * Initialize local bus.
71 initdram(int board_type)
75 puts("Initializing\n");
77 #if defined(CONFIG_DDR_DLL)
79 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
83 * Work around to stabilize DDR DLL
85 temp_ddrdll = gur->ddrdllcr;
86 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
87 asm("sync;isync;msync");
91 #if defined(CONFIG_SPD_EEPROM)
92 dram_size = spd_sdram ();
94 dram_size = fixed_sdram ();
97 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
99 * Initialize and enable DDR ECC.
101 ddr_enable_ecc(dram_size);
115 * Initialize Local Bus
121 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
122 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
130 * Fix Local Bus clock glitch when DLL is enabled.
132 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
133 * If localbus freq is > 133Mhz, DLL can be safely enabled.
134 * Between 66 and 133, the DLL is enabled with an override workaround.
137 get_sys_info(&sysinfo);
138 clkdiv = lbc->lcrr & 0x0f;
139 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
142 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
144 } else if (lbc_hz >= 133) {
145 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
149 * On REV1 boards, need to change CLKDIV before enable DLL.
150 * Default CLKDIV is 8, change it to 4 temporarily.
152 uint pvr = get_pvr();
153 uint temp_lbcdll = 0;
155 if (pvr == PVR_85xx_REV1) {
156 /* FIXME: Justify the high bit here. */
157 lbc->lcrr = 0x10000004;
160 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
164 * Sample LBC DLL ctrl reg, upshift it to set the
167 temp_lbcdll = gur->lbcdllcr;
168 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
169 asm("sync;isync;msync");
175 * Initialize SDRAM memory on the Local Bus.
181 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
182 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
185 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
188 * Setup SDRAM Base and Option Registers
190 lbc->or2 = CFG_OR2_PRELIM;
191 lbc->br2 = CFG_BR2_PRELIM;
192 lbc->lbcr = CFG_LBC_LBCR;
195 lbc->lsrt = CFG_LBC_LSRT;
196 lbc->mrtpr = CFG_LBC_MRTPR;
200 * Configure the SDRAM controller.
202 lbc->lsdmr = CFG_LBC_LSDMR_1;
205 ppcDcbf((unsigned long) sdram_addr);
208 lbc->lsdmr = CFG_LBC_LSDMR_2;
211 ppcDcbf((unsigned long) sdram_addr);
214 lbc->lsdmr = CFG_LBC_LSDMR_3;
217 ppcDcbf((unsigned long) sdram_addr);
220 lbc->lsdmr = CFG_LBC_LSDMR_4;
223 ppcDcbf((unsigned long) sdram_addr);
226 lbc->lsdmr = CFG_LBC_LSDMR_5;
229 ppcDcbf((unsigned long) sdram_addr);
233 #if !defined(CONFIG_SPD_EEPROM)
234 /*************************************************************************
235 * fixed sdram init -- doesn't use serial presence detect.
236 ************************************************************************/
237 long int fixed_sdram (void)
240 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
242 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
243 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
244 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
245 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
246 ddr->sdram_mode = CFG_DDR_MODE;
247 ddr->sdram_interval = CFG_DDR_INTERVAL;
248 #if defined (CONFIG_DDR_ECC)
249 ddr->err_disable = 0x0000000D;
250 ddr->err_sbe = 0x00ff0000;
252 asm("sync;isync;msync");
254 #if defined (CONFIG_DDR_ECC)
255 /* Enable ECC checking */
256 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
258 ddr->sdram_cfg = CFG_DDR_CONTROL;
260 asm("sync; isync; msync");
263 return CFG_SDRAM_SIZE * 1024 * 1024;
265 #endif /* !defined(CONFIG_SPD_EEPROM) */
268 #if defined(CONFIG_PCI)
270 * Initialize PCI Devices, report devices found.
274 static struct pci_controller hose;
276 #endif /* CONFIG_PCI */
283 pci_mpc85xx_init(&hose);
284 #endif /* CONFIG_PCI */
288 #if defined(CONFIG_OF_BOARD_SETUP)
290 ft_board_setup(void *blob, bd_t *bd)
295 ft_cpu_setup(blob, bd);
297 node = fdt_path_offset(blob, "/aliases");
301 path = fdt_getprop(blob, node, "pci0", NULL);
303 tmp[1] = hose.last_busno - hose.first_busno;
304 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);