2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/immap_fsl_pci.h>
33 #include <fdt_support.h>
35 #include "../common/pixis.h"
37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38 extern void ddr_enable_ecc(unsigned int dram_size);
41 extern long int spd_sdram(void);
43 void sdram_init(void);
45 int board_early_init_f (void)
52 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
53 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
54 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
56 if ((uint)&gur->porpllsr != 0xe00e0000) {
57 printf("immap size error %x\n",&gur->porpllsr);
59 printf ("Board: MPC8544DS\n");
61 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
62 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
63 ecm->eedr = 0xffffffff; /* Clear ecm errors */
64 ecm->eeer = 0xffffffff; /* Enable ecm errors */
70 initdram(int board_type)
74 puts("Initializing\n");
76 dram_size = spd_sdram();
78 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
80 * Initialize and enable DDR ECC.
82 ddr_enable_ecc(dram_size);
88 #if defined(CFG_DRAM_TEST)
92 uint *pstart = (uint *) CFG_MEMTEST_START;
93 uint *pend = (uint *) CFG_MEMTEST_END;
96 printf("Testing DRAM from 0x%08x to 0x%08x\n",
100 printf("DRAM test phase 1:\n");
101 for (p = pstart; p < pend; p++)
104 for (p = pstart; p < pend; p++) {
105 if (*p != 0xaaaaaaaa) {
106 printf ("DRAM test fails at: %08x\n", (uint) p);
111 printf("DRAM test phase 2:\n");
112 for (p = pstart; p < pend; p++)
115 for (p = pstart; p < pend; p++) {
116 if (*p != 0x55555555) {
117 printf ("DRAM test fails at: %08x\n", (uint) p);
122 printf("DRAM test passed.\n");
128 static struct pci_controller pci1_hose;
132 static struct pci_controller pcie1_hose;
136 static struct pci_controller pcie2_hose;
140 static struct pci_controller pcie3_hose;
143 int first_free_busno=0;
148 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
149 uint devdisr = gur->devdisr;
150 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
151 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
153 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
154 devdisr, io_sel, host_agent);
157 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
158 printf (" eTSEC1 is in sgmii mode.\n");
159 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
160 printf (" eTSEC3 is in sgmii mode.\n");
165 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
166 extern void fsl_pci_init(struct pci_controller *hose);
167 struct pci_controller *hose = &pcie3_hose;
168 int pcie_ep = (host_agent == 3);
169 int pcie_configured = io_sel >= 1;
171 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
172 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
173 pcie_ep ? "End Point" : "Root Complex",
175 if (pci->pme_msg_det) {
176 pci->pme_msg_det = 0xffffffff;
177 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
182 pci_set_region(hose->regions + 0,
186 PCI_REGION_MEM | PCI_REGION_MEMORY);
188 /* outbound memory */
189 pci_set_region(hose->regions + 1,
196 pci_set_region(hose->regions + 2,
202 hose->region_count = 3;
203 #ifdef CFG_PCIE3_MEM_BASE2
204 /* outbound memory */
205 pci_set_region(hose->regions + 3,
210 hose->region_count++;
212 hose->first_busno=first_free_busno;
213 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
217 first_free_busno=hose->last_busno+1;
218 printf (" PCIE3 on bus %02x - %02x\n",
219 hose->first_busno,hose->last_busno);
222 * Activate ULI1575 legacy chip by performing a fake
223 * memory access. Needed to make ULI RTC work.
225 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
227 printf (" PCIE3: disabled\n");
232 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
237 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
238 extern void fsl_pci_init(struct pci_controller *hose);
239 struct pci_controller *hose = &pcie1_hose;
240 int pcie_ep = (host_agent == 5);
241 int pcie_configured = io_sel & 6;
243 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
244 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
245 pcie_ep ? "End Point" : "Root Complex",
247 if (pci->pme_msg_det) {
248 pci->pme_msg_det = 0xffffffff;
249 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
254 pci_set_region(hose->regions + 0,
258 PCI_REGION_MEM | PCI_REGION_MEMORY);
260 /* outbound memory */
261 pci_set_region(hose->regions + 1,
268 pci_set_region(hose->regions + 2,
274 hose->region_count = 3;
275 #ifdef CFG_PCIE1_MEM_BASE2
276 /* outbound memory */
277 pci_set_region(hose->regions + 3,
282 hose->region_count++;
284 hose->first_busno=first_free_busno;
286 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
290 first_free_busno=hose->last_busno+1;
291 printf(" PCIE1 on bus %02x - %02x\n",
292 hose->first_busno,hose->last_busno);
295 printf (" PCIE1: disabled\n");
300 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
305 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
306 extern void fsl_pci_init(struct pci_controller *hose);
307 struct pci_controller *hose = &pcie2_hose;
308 int pcie_ep = (host_agent == 3);
309 int pcie_configured = io_sel & 4;
311 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
312 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
313 pcie_ep ? "End Point" : "Root Complex",
315 if (pci->pme_msg_det) {
316 pci->pme_msg_det = 0xffffffff;
317 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
322 pci_set_region(hose->regions + 0,
326 PCI_REGION_MEM | PCI_REGION_MEMORY);
328 /* outbound memory */
329 pci_set_region(hose->regions + 1,
336 pci_set_region(hose->regions + 2,
342 hose->region_count = 3;
343 #ifdef CFG_PCIE2_MEM_BASE2
344 /* outbound memory */
345 pci_set_region(hose->regions + 3,
350 hose->region_count++;
352 hose->first_busno=first_free_busno;
353 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
356 first_free_busno=hose->last_busno+1;
357 printf (" PCIE2 on bus %02x - %02x\n",
358 hose->first_busno,hose->last_busno);
361 printf (" PCIE2: disabled\n");
366 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
372 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
373 extern void fsl_pci_init(struct pci_controller *hose);
374 struct pci_controller *hose = &pci1_hose;
376 uint pci_agent = (host_agent == 6);
377 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
379 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
380 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
383 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
384 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
386 (pci_speed == 33333000) ? "33" :
387 (pci_speed == 66666000) ? "66" : "unknown",
388 pci_clk_sel ? "sync" : "async",
389 pci_agent ? "agent" : "host",
390 pci_arb ? "arbiter" : "external-arbiter",
395 pci_set_region(hose->regions + 0,
399 PCI_REGION_MEM | PCI_REGION_MEMORY);
401 /* outbound memory */
402 pci_set_region(hose->regions + 1,
409 pci_set_region(hose->regions + 2,
414 hose->region_count = 3;
415 #ifdef CFG_PCIE3_MEM_BASE2
416 /* outbound memory */
417 pci_set_region(hose->regions + 3,
422 hose->region_count++;
424 hose->first_busno=first_free_busno;
425 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
428 first_free_busno=hose->last_busno+1;
429 printf ("PCI on bus %02x - %02x\n",
430 hose->first_busno,hose->last_busno);
432 printf (" PCI: disabled\n");
436 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
441 int last_stage_init(void)
448 get_board_sys_clk(ulong dummy)
450 u8 i, go_bit, rd_clks;
453 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
456 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
460 * Only if both go bit and the SCLK bit in VCFGEN0 are set
461 * should we be using the AUX register. Remember, we also set the
462 * GO bit to boot from the alternate bank on the on-board flash
467 i = in8(PIXIS_BASE + PIXIS_AUX);
469 i = in8(PIXIS_BASE + PIXIS_SPD);
471 i = in8(PIXIS_BASE + PIXIS_SPD);
506 #if defined(CONFIG_OF_BOARD_SETUP)
509 ft_board_setup(void *blob, bd_t *bd)
514 ft_cpu_setup(blob, bd);
516 node = fdt_path_offset(blob, "/aliases");
520 path = fdt_getprop(blob, node, "pci0", NULL);
522 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
523 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
527 path = fdt_getprop(blob, node, "pci1", NULL);
529 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
530 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
534 path = fdt_getprop(blob, node, "pci2", NULL);
536 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
537 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
541 path = fdt_getprop(blob, node, "pci3", NULL);
543 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
544 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);