2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/immap_fsl_pci.h>
33 #include "../common/pixis.h"
35 #if defined(CONFIG_OF_FLAT_TREE)
37 extern void ft_cpu_setup(void *blob, bd_t *bd);
40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
41 extern void ddr_enable_ecc(unsigned int dram_size);
44 extern long int spd_sdram(void);
46 void sdram_init(void);
48 int board_early_init_f (void)
55 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
56 volatile ccsr_gur_t *gur = &immap->im_gur;
57 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
58 volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
60 if ((uint)&gur->porpllsr != 0xe00e0000) {
61 printf("immap size error %x\n",&gur->porpllsr);
63 printf ("Board: MPC8544DS\n");
65 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
66 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
67 ecm->eedr = 0xffffffff; /* Clear ecm errors */
68 ecm->eeer = 0xffffffff; /* Enable ecm errors */
74 initdram(int board_type)
78 puts("Initializing\n");
80 dram_size = spd_sdram();
82 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
84 * Initialize and enable DDR ECC.
86 ddr_enable_ecc(dram_size);
92 #if defined(CFG_DRAM_TEST)
96 uint *pstart = (uint *) CFG_MEMTEST_START;
97 uint *pend = (uint *) CFG_MEMTEST_END;
100 printf("Testing DRAM from 0x%08x to 0x%08x\n",
104 printf("DRAM test phase 1:\n");
105 for (p = pstart; p < pend; p++)
108 for (p = pstart; p < pend; p++) {
109 if (*p != 0xaaaaaaaa) {
110 printf ("DRAM test fails at: %08x\n", (uint) p);
115 printf("DRAM test phase 2:\n");
116 for (p = pstart; p < pend; p++)
119 for (p = pstart; p < pend; p++) {
120 if (*p != 0x55555555) {
121 printf ("DRAM test fails at: %08x\n", (uint) p);
126 printf("DRAM test passed.\n");
132 static struct pci_controller pci1_hose;
136 static struct pci_controller pcie1_hose;
140 static struct pci_controller pcie2_hose;
144 static struct pci_controller pcie3_hose;
147 int first_free_busno=0;
152 volatile immap_t *immap = (immap_t *)CFG_IMMR;
153 volatile ccsr_gur_t *gur = &immap->im_gur;
154 uint devdisr = gur->devdisr;
155 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
156 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
158 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
159 devdisr, io_sel, host_agent);
162 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
163 printf (" eTSEC1 is in sgmii mode.\n");
164 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
165 printf (" eTSEC3 is in sgmii mode.\n");
170 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
171 extern void fsl_pci_init(struct pci_controller *hose);
172 struct pci_controller *hose = &pcie3_hose;
173 int pcie_ep = (host_agent == 3);
174 int pcie_configured = io_sel >= 1;
176 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
177 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
178 pcie_ep ? "End Point" : "Root Complex",
180 if (pci->pme_msg_det) {
181 pci->pme_msg_det = 0xffffffff;
182 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
187 pci_set_region(hose->regions + 0,
191 PCI_REGION_MEM | PCI_REGION_MEMORY);
193 /* outbound memory */
194 pci_set_region(hose->regions + 1,
201 pci_set_region(hose->regions + 2,
207 hose->region_count = 3;
208 #ifdef CFG_PCIE3_MEM_BASE2
209 /* outbound memory */
210 pci_set_region(hose->regions + 3,
215 hose->region_count++;
217 hose->first_busno=first_free_busno;
218 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
222 first_free_busno=hose->last_busno+1;
223 printf (" PCIE3 on bus %02x - %02x\n",
224 hose->first_busno,hose->last_busno);
227 * Activate ULI1575 legacy chip by performing a fake
228 * memory access. Needed to make ULI RTC work.
230 in_be32(CFG_PCIE3_MEM_BASE);
232 printf (" PCIE3: disabled\n");
237 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
242 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
243 extern void fsl_pci_init(struct pci_controller *hose);
244 struct pci_controller *hose = &pcie1_hose;
245 int pcie_ep = (host_agent == 5);
246 int pcie_configured = io_sel & 6;
248 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
249 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
250 pcie_ep ? "End Point" : "Root Complex",
252 if (pci->pme_msg_det) {
253 pci->pme_msg_det = 0xffffffff;
254 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
259 pci_set_region(hose->regions + 0,
263 PCI_REGION_MEM | PCI_REGION_MEMORY);
265 /* outbound memory */
266 pci_set_region(hose->regions + 1,
273 pci_set_region(hose->regions + 2,
279 hose->region_count = 3;
280 #ifdef CFG_PCIE1_MEM_BASE2
281 /* outbound memory */
282 pci_set_region(hose->regions + 3,
287 hose->region_count++;
289 hose->first_busno=first_free_busno;
291 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
295 first_free_busno=hose->last_busno+1;
296 printf(" PCIE1 on bus %02x - %02x\n",
297 hose->first_busno,hose->last_busno);
300 printf (" PCIE1: disabled\n");
305 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
310 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
311 extern void fsl_pci_init(struct pci_controller *hose);
312 struct pci_controller *hose = &pcie2_hose;
313 int pcie_ep = (host_agent == 3);
314 int pcie_configured = io_sel & 4;
316 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
317 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
318 pcie_ep ? "End Point" : "Root Complex",
320 if (pci->pme_msg_det) {
321 pci->pme_msg_det = 0xffffffff;
322 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
327 pci_set_region(hose->regions + 0,
331 PCI_REGION_MEM | PCI_REGION_MEMORY);
333 /* outbound memory */
334 pci_set_region(hose->regions + 1,
341 pci_set_region(hose->regions + 2,
347 hose->region_count = 3;
348 #ifdef CFG_PCIE2_MEM_BASE2
349 /* outbound memory */
350 pci_set_region(hose->regions + 3,
355 hose->region_count++;
357 hose->first_busno=first_free_busno;
358 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
361 first_free_busno=hose->last_busno+1;
362 printf (" PCIE2 on bus %02x - %02x\n",
363 hose->first_busno,hose->last_busno);
366 printf (" PCIE2: disabled\n");
371 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
377 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
378 extern void fsl_pci_init(struct pci_controller *hose);
379 struct pci_controller *hose = &pci1_hose;
381 uint pci_agent = (host_agent == 6);
382 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
384 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
385 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
388 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
389 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
391 (pci_speed == 33333000) ? "33" :
392 (pci_speed == 66666000) ? "66" : "unknown",
393 pci_clk_sel ? "sync" : "async",
394 pci_agent ? "agent" : "host",
395 pci_arb ? "arbiter" : "external-arbiter",
400 pci_set_region(hose->regions + 0,
404 PCI_REGION_MEM | PCI_REGION_MEMORY);
406 /* outbound memory */
407 pci_set_region(hose->regions + 1,
414 pci_set_region(hose->regions + 2,
419 hose->region_count = 3;
420 #ifdef CFG_PCIE3_MEM_BASE2
421 /* outbound memory */
422 pci_set_region(hose->regions + 3,
427 hose->region_count++;
429 hose->first_busno=first_free_busno;
430 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
433 first_free_busno=hose->last_busno+1;
434 printf ("PCI on bus %02x - %02x\n",
435 hose->first_busno,hose->last_busno);
437 printf (" PCI: disabled\n");
441 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
446 int last_stage_init(void)
453 get_board_sys_clk(ulong dummy)
455 u8 i, go_bit, rd_clks;
458 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
461 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
465 * Only if both go bit and the SCLK bit in VCFGEN0 are set
466 * should we be using the AUX register. Remember, we also set the
467 * GO bit to boot from the alternate bank on the on-board flash
472 i = in8(PIXIS_BASE + PIXIS_AUX);
474 i = in8(PIXIS_BASE + PIXIS_SPD);
476 i = in8(PIXIS_BASE + PIXIS_SPD);
511 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
513 ft_board_setup(void *blob, bd_t *bd)
518 ft_cpu_setup(blob, bd);
520 p = ft_get_prop(blob, "/memory/reg", &len);
522 *p++ = cpu_to_be32(bd->bi_memstart);
523 *p = cpu_to_be32(bd->bi_memsize);
526 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
529 p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
530 debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
534 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
537 p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
538 debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
542 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
545 p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
546 debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
550 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
553 p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
554 debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);