2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
43 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
45 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
47 if ((uint)&gur->porpllsr != 0xe00e0000) {
48 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
50 printf ("Board: MPC8544DS, System ID: 0x%02x, "
51 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
52 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
53 in8(PIXIS_BASE + PIXIS_PVER));
55 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
56 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
57 ecm->eedr = 0xffffffff; /* Clear ecm errors */
58 ecm->eeer = 0xffffffff; /* Enable ecm errors */
64 initdram(int board_type)
68 puts("Initializing\n");
70 dram_size = fsl_ddr_sdram();
72 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
74 dram_size *= 0x100000;
81 static struct pci_controller pci1_hose;
85 static struct pci_controller pcie1_hose;
89 static struct pci_controller pcie2_hose;
93 static struct pci_controller pcie3_hose;
96 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
97 extern void fsl_pci_init(struct pci_controller *hose);
99 int first_free_busno=0;
104 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
105 uint devdisr = gur->devdisr;
106 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
107 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
109 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
110 devdisr, io_sel, host_agent);
113 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
114 printf (" eTSEC1 is in sgmii mode.\n");
115 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
116 printf (" eTSEC3 is in sgmii mode.\n");
121 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
122 struct pci_controller *hose = &pcie3_hose;
123 int pcie_ep = (host_agent == 1);
124 int pcie_configured = io_sel >= 6;
125 struct pci_region *r = hose->regions;
127 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
128 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
129 pcie_ep ? "End Point" : "Root Complex",
131 if (pci->pme_msg_det) {
132 pci->pme_msg_det = 0xffffffff;
133 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
138 r += fsl_pci_setup_inbound_windows(r);
140 /* outbound memory */
142 CONFIG_SYS_PCIE3_MEM_BUS,
143 CONFIG_SYS_PCIE3_MEM_PHYS,
144 CONFIG_SYS_PCIE3_MEM_SIZE,
149 CONFIG_SYS_PCIE3_IO_BUS,
150 CONFIG_SYS_PCIE3_IO_PHYS,
151 CONFIG_SYS_PCIE3_IO_SIZE,
154 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
155 /* outbound memory */
157 CONFIG_SYS_PCIE3_MEM_BUS2,
158 CONFIG_SYS_PCIE3_MEM_PHYS2,
159 CONFIG_SYS_PCIE3_MEM_SIZE2,
162 hose->region_count = r - hose->regions;
163 hose->first_busno=first_free_busno;
164 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
168 first_free_busno=hose->last_busno+1;
169 printf (" PCIE3 on bus %02x - %02x\n",
170 hose->first_busno,hose->last_busno);
173 * Activate ULI1575 legacy chip by performing a fake
174 * memory access. Needed to make ULI RTC work.
176 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
178 printf (" PCIE3: disabled\n");
183 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
188 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
189 struct pci_controller *hose = &pcie1_hose;
190 int pcie_ep = (host_agent == 5);
191 int pcie_configured = io_sel >= 2;
192 struct pci_region *r = hose->regions;
194 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
195 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
196 pcie_ep ? "End Point" : "Root Complex",
198 if (pci->pme_msg_det) {
199 pci->pme_msg_det = 0xffffffff;
200 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
205 r += fsl_pci_setup_inbound_windows(r);
207 /* outbound memory */
209 CONFIG_SYS_PCIE1_MEM_BUS,
210 CONFIG_SYS_PCIE1_MEM_PHYS,
211 CONFIG_SYS_PCIE1_MEM_SIZE,
216 CONFIG_SYS_PCIE1_IO_BUS,
217 CONFIG_SYS_PCIE1_IO_PHYS,
218 CONFIG_SYS_PCIE1_IO_SIZE,
221 #ifdef CONFIG_SYS_PCIE1_MEM_BUS2
222 /* outbound memory */
224 CONFIG_SYS_PCIE1_MEM_BUS2,
225 CONFIG_SYS_PCIE1_MEM_PHYS2,
226 CONFIG_SYS_PCIE1_MEM_SIZE2,
229 hose->region_count = r - hose->regions;
230 hose->first_busno=first_free_busno;
232 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
236 first_free_busno=hose->last_busno+1;
237 printf(" PCIE1 on bus %02x - %02x\n",
238 hose->first_busno,hose->last_busno);
241 printf (" PCIE1: disabled\n");
246 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
251 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
252 struct pci_controller *hose = &pcie2_hose;
253 int pcie_ep = (host_agent == 3);
254 int pcie_configured = io_sel >= 4;
255 struct pci_region *r = hose->regions;
257 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
258 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
259 pcie_ep ? "End Point" : "Root Complex",
261 if (pci->pme_msg_det) {
262 pci->pme_msg_det = 0xffffffff;
263 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
268 r += fsl_pci_setup_inbound_windows(r);
270 /* outbound memory */
272 CONFIG_SYS_PCIE2_MEM_BUS,
273 CONFIG_SYS_PCIE2_MEM_PHYS,
274 CONFIG_SYS_PCIE2_MEM_SIZE,
279 CONFIG_SYS_PCIE2_IO_BUS,
280 CONFIG_SYS_PCIE2_IO_PHYS,
281 CONFIG_SYS_PCIE2_IO_SIZE,
284 #ifdef CONFIG_SYS_PCIE2_MEM_BUS2
285 /* outbound memory */
287 CONFIG_SYS_PCIE2_MEM_BUS2,
288 CONFIG_SYS_PCIE2_MEM_PHYS2,
289 CONFIG_SYS_PCIE2_MEM_SIZE2,
292 hose->region_count = r - hose->regions;
293 hose->first_busno=first_free_busno;
294 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
297 first_free_busno=hose->last_busno+1;
298 printf (" PCIE2 on bus %02x - %02x\n",
299 hose->first_busno,hose->last_busno);
302 printf (" PCIE2: disabled\n");
307 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
313 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
314 struct pci_controller *hose = &pci1_hose;
315 struct pci_region *r = hose->regions;
317 uint pci_agent = (host_agent == 6);
318 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
320 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
321 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
324 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
325 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
327 (pci_speed == 33333000) ? "33" :
328 (pci_speed == 66666000) ? "66" : "unknown",
329 pci_clk_sel ? "sync" : "async",
330 pci_agent ? "agent" : "host",
331 pci_arb ? "arbiter" : "external-arbiter",
336 r += fsl_pci_setup_inbound_windows(r);
338 /* outbound memory */
340 CONFIG_SYS_PCI1_MEM_BUS,
341 CONFIG_SYS_PCI1_MEM_PHYS,
342 CONFIG_SYS_PCI1_MEM_SIZE,
347 CONFIG_SYS_PCI1_IO_BUS,
348 CONFIG_SYS_PCI1_IO_PHYS,
349 CONFIG_SYS_PCI1_IO_SIZE,
352 #ifdef CONFIG_SYS_PCIE3_MEM_BUS2
353 /* outbound memory */
355 CONFIG_SYS_PCIE3_MEM_BUS2,
356 CONFIG_SYS_PCIE3_MEM_PHYS2,
357 CONFIG_SYS_PCIE3_MEM_SIZE2,
360 hose->region_count = r - hose->regions;
361 hose->first_busno=first_free_busno;
362 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
365 first_free_busno=hose->last_busno+1;
366 printf ("PCI on bus %02x - %02x\n",
367 hose->first_busno,hose->last_busno);
369 printf (" PCI: disabled\n");
373 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
378 int last_stage_init(void)
385 get_board_sys_clk(ulong dummy)
387 u8 i, go_bit, rd_clks;
390 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
393 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
397 * Only if both go bit and the SCLK bit in VCFGEN0 are set
398 * should we be using the AUX register. Remember, we also set the
399 * GO bit to boot from the alternate bank on the on-board flash
404 i = in8(PIXIS_BASE + PIXIS_AUX);
406 i = in8(PIXIS_BASE + PIXIS_SPD);
408 i = in8(PIXIS_BASE + PIXIS_SPD);
443 int board_eth_init(bd_t *bis)
445 #ifdef CONFIG_TSEC_ENET
446 struct tsec_info_struct tsec_info[2];
447 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
448 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
452 SET_STD_TSEC_INFO(tsec_info[num], 1);
453 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
454 tsec_info[num].flags |= TSEC_SGMII;
458 SET_STD_TSEC_INFO(tsec_info[num], 3);
459 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
460 tsec_info[num].flags |= TSEC_SGMII;
465 printf("No TSECs initialized\n");
471 fsl_sgmii_riser_init(tsec_info, num);
474 tsec_eth_init(bis, tsec_info, num);
476 return pci_eth_init(bis);
479 #if defined(CONFIG_OF_BOARD_SETUP)
480 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
481 struct pci_controller *hose);
483 void ft_board_setup(void *blob, bd_t *bd)
485 ft_cpu_setup(blob, bd);
489 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
492 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
495 ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
498 ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);