2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
30 #include <asm/fsl_ddr_sdram.h>
34 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42 extern void ddr_enable_ecc(unsigned int dram_size);
47 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
48 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
49 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
51 if ((uint)&gur->porpllsr != 0xe00e0000) {
52 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
54 printf ("Board: MPC8544DS, System ID: 0x%02x, "
55 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
56 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
57 in8(PIXIS_BASE + PIXIS_PVER));
59 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
60 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
61 ecm->eedr = 0xffffffff; /* Clear ecm errors */
62 ecm->eeer = 0xffffffff; /* Enable ecm errors */
68 initdram(int board_type)
72 puts("Initializing\n");
74 dram_size = fsl_ddr_sdram();
76 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
78 dram_size *= 0x100000;
80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
82 * Initialize and enable DDR ECC.
84 ddr_enable_ecc(dram_size);
91 static struct pci_controller pci1_hose;
95 static struct pci_controller pcie1_hose;
99 static struct pci_controller pcie2_hose;
103 static struct pci_controller pcie3_hose;
106 int first_free_busno=0;
111 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
112 uint devdisr = gur->devdisr;
113 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
114 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
116 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
117 devdisr, io_sel, host_agent);
120 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
121 printf (" eTSEC1 is in sgmii mode.\n");
122 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
123 printf (" eTSEC3 is in sgmii mode.\n");
128 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
129 extern void fsl_pci_init(struct pci_controller *hose);
130 struct pci_controller *hose = &pcie3_hose;
131 int pcie_ep = (host_agent == 1);
132 int pcie_configured = io_sel >= 1;
134 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
135 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
136 pcie_ep ? "End Point" : "Root Complex",
138 if (pci->pme_msg_det) {
139 pci->pme_msg_det = 0xffffffff;
140 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
145 pci_set_region(hose->regions + 0,
149 PCI_REGION_MEM | PCI_REGION_MEMORY);
151 /* outbound memory */
152 pci_set_region(hose->regions + 1,
159 pci_set_region(hose->regions + 2,
165 hose->region_count = 3;
166 #ifdef CFG_PCIE3_MEM_BASE2
167 /* outbound memory */
168 pci_set_region(hose->regions + 3,
173 hose->region_count++;
175 hose->first_busno=first_free_busno;
176 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
180 first_free_busno=hose->last_busno+1;
181 printf (" PCIE3 on bus %02x - %02x\n",
182 hose->first_busno,hose->last_busno);
185 * Activate ULI1575 legacy chip by performing a fake
186 * memory access. Needed to make ULI RTC work.
188 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
190 printf (" PCIE3: disabled\n");
195 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
200 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
201 extern void fsl_pci_init(struct pci_controller *hose);
202 struct pci_controller *hose = &pcie1_hose;
203 int pcie_ep = (host_agent == 5);
204 int pcie_configured = io_sel & 6;
206 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
207 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
208 pcie_ep ? "End Point" : "Root Complex",
210 if (pci->pme_msg_det) {
211 pci->pme_msg_det = 0xffffffff;
212 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
217 pci_set_region(hose->regions + 0,
221 PCI_REGION_MEM | PCI_REGION_MEMORY);
223 /* outbound memory */
224 pci_set_region(hose->regions + 1,
231 pci_set_region(hose->regions + 2,
237 hose->region_count = 3;
238 #ifdef CFG_PCIE1_MEM_BASE2
239 /* outbound memory */
240 pci_set_region(hose->regions + 3,
245 hose->region_count++;
247 hose->first_busno=first_free_busno;
249 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
253 first_free_busno=hose->last_busno+1;
254 printf(" PCIE1 on bus %02x - %02x\n",
255 hose->first_busno,hose->last_busno);
258 printf (" PCIE1: disabled\n");
263 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
268 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
269 extern void fsl_pci_init(struct pci_controller *hose);
270 struct pci_controller *hose = &pcie2_hose;
271 int pcie_ep = (host_agent == 3);
272 int pcie_configured = io_sel & 4;
274 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
275 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
276 pcie_ep ? "End Point" : "Root Complex",
278 if (pci->pme_msg_det) {
279 pci->pme_msg_det = 0xffffffff;
280 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
285 pci_set_region(hose->regions + 0,
289 PCI_REGION_MEM | PCI_REGION_MEMORY);
291 /* outbound memory */
292 pci_set_region(hose->regions + 1,
299 pci_set_region(hose->regions + 2,
305 hose->region_count = 3;
306 #ifdef CFG_PCIE2_MEM_BASE2
307 /* outbound memory */
308 pci_set_region(hose->regions + 3,
313 hose->region_count++;
315 hose->first_busno=first_free_busno;
316 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
319 first_free_busno=hose->last_busno+1;
320 printf (" PCIE2 on bus %02x - %02x\n",
321 hose->first_busno,hose->last_busno);
324 printf (" PCIE2: disabled\n");
329 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
335 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
336 extern void fsl_pci_init(struct pci_controller *hose);
337 struct pci_controller *hose = &pci1_hose;
339 uint pci_agent = (host_agent == 6);
340 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
342 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
343 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
346 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
347 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
349 (pci_speed == 33333000) ? "33" :
350 (pci_speed == 66666000) ? "66" : "unknown",
351 pci_clk_sel ? "sync" : "async",
352 pci_agent ? "agent" : "host",
353 pci_arb ? "arbiter" : "external-arbiter",
358 pci_set_region(hose->regions + 0,
362 PCI_REGION_MEM | PCI_REGION_MEMORY);
364 /* outbound memory */
365 pci_set_region(hose->regions + 1,
372 pci_set_region(hose->regions + 2,
377 hose->region_count = 3;
378 #ifdef CFG_PCIE3_MEM_BASE2
379 /* outbound memory */
380 pci_set_region(hose->regions + 3,
385 hose->region_count++;
387 hose->first_busno=first_free_busno;
388 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
391 first_free_busno=hose->last_busno+1;
392 printf ("PCI on bus %02x - %02x\n",
393 hose->first_busno,hose->last_busno);
395 printf (" PCI: disabled\n");
399 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
404 int last_stage_init(void)
411 get_board_sys_clk(ulong dummy)
413 u8 i, go_bit, rd_clks;
416 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
419 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
423 * Only if both go bit and the SCLK bit in VCFGEN0 are set
424 * should we be using the AUX register. Remember, we also set the
425 * GO bit to boot from the alternate bank on the on-board flash
430 i = in8(PIXIS_BASE + PIXIS_AUX);
432 i = in8(PIXIS_BASE + PIXIS_SPD);
434 i = in8(PIXIS_BASE + PIXIS_SPD);
469 int board_eth_init(bd_t *bis)
471 #ifdef CONFIG_TSEC_ENET
472 struct tsec_info_struct tsec_info[2];
473 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
474 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
478 SET_STD_TSEC_INFO(tsec_info[num], 1);
479 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
480 tsec_info[num].flags |= TSEC_SGMII;
484 SET_STD_TSEC_INFO(tsec_info[num], 3);
485 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
486 tsec_info[num].flags |= TSEC_SGMII;
491 printf("No TSECs initialized\n");
497 fsl_sgmii_riser_init(tsec_info, num);
500 tsec_eth_init(bis, tsec_info, num);
502 return pci_eth_init(bis);
505 #if defined(CONFIG_OF_BOARD_SETUP)
508 ft_board_setup(void *blob, bd_t *bd)
513 ft_cpu_setup(blob, bd);
515 node = fdt_path_offset(blob, "/aliases");
519 path = fdt_getprop(blob, node, "pci0", NULL);
521 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
522 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
526 path = fdt_getprop(blob, node, "pci1", NULL);
528 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
529 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
533 path = fdt_getprop(blob, node, "pci2", NULL);
535 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
536 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
540 path = fdt_getprop(blob, node, "pci3", NULL);
542 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
543 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);