2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
32 #include <asm/immap_85xx.h>
33 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
38 #include <fdt_support.h>
39 #include <asm/fsl_lbc.h>
41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42 extern void ddr_enable_ecc(unsigned int dram_size);
46 void local_bus_init(void);
47 void sdram_init(void);
48 long int fixed_sdram(void);
52 * I/O Port configuration table
54 * if conf is 1, then that port pin will be configured at boot time
55 * according to the five values podr/pdir/ppar/psor/pdat for that entry
58 const iop_conf_t iop_conf_tab[4][32] = {
60 /* Port A configuration */
61 { /* conf ppar psor pdir podr pdat */
62 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
63 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
64 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
65 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
66 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
67 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
68 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
69 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
70 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
71 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
72 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
73 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
74 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
75 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
76 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
77 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
78 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
79 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
80 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
81 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
82 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
83 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
84 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
85 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
86 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
87 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
88 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
89 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
90 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
91 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
92 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
93 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
96 /* Port B configuration */
97 { /* conf ppar psor pdir podr pdat */
98 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
99 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
100 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
101 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
102 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
103 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
104 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
105 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
106 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
107 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
108 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
109 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
110 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
111 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
112 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
113 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
114 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
115 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
116 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
117 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
118 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
119 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
120 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
121 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
122 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
123 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
124 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
125 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
126 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
128 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
129 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
133 { /* conf ppar psor pdir podr pdat */
134 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
135 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
136 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
137 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
138 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
139 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
140 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
141 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
142 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
143 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
144 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
145 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
146 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
147 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
148 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
149 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
150 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
151 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
152 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
153 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
154 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
155 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
156 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
157 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
158 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
159 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
160 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
161 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
162 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
163 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
164 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
165 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
169 { /* conf ppar psor pdir podr pdat */
170 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
171 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
172 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
173 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
174 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
175 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
176 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
177 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
178 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
179 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
180 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
181 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
182 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
183 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
184 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
185 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
186 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
187 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
188 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
189 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
190 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
191 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
192 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
193 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
194 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
195 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
196 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
197 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
198 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
199 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
200 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
201 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
207 * MPC8560ADS Board Status & Control Registers
209 typedef struct bcsr_ {
210 volatile unsigned char bcsr0;
211 volatile unsigned char bcsr1;
212 volatile unsigned char bcsr2;
213 volatile unsigned char bcsr3;
214 volatile unsigned char bcsr4;
215 volatile unsigned char bcsr5;
218 void reset_phy (void)
220 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
221 volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
223 /* reset Giga bit Ethernet port if needed here */
225 /* reset the CPM FEC port */
226 #if (CONFIG_ETHER_INDEX == 2)
227 bcsr->bcsr2 &= ~FETH2_RST;
229 bcsr->bcsr2 |= FETH2_RST;
231 #elif (CONFIG_ETHER_INDEX == 3)
232 bcsr->bcsr3 &= ~FETH3_RST;
234 bcsr->bcsr3 |= FETH3_RST;
237 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
239 miiphy_reset("FCC1", 0x0);
241 /* change PHY address to 0x02 */
242 bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
244 bb_miiphy_write(NULL, 0x02, PHY_BMCR,
245 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
246 #endif /* CONFIG_MII */
250 int checkboard (void)
252 puts("Board: ADS\n");
255 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
256 CONFIG_SYS_CLK_FREQ / 1000000);
258 printf(" PCI1: disabled\n");
262 * Initialize local bus.
271 initdram(int board_type)
275 puts("Initializing\n");
277 #if defined(CONFIG_DDR_DLL)
279 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
280 uint temp_ddrdll = 0;
283 * Work around to stabilize DDR DLL
285 temp_ddrdll = gur->ddrdllcr;
286 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
287 asm("sync;isync;msync");
291 #ifdef CONFIG_SPD_EEPROM
292 dram_size = fsl_ddr_sdram();
293 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
295 dram_size *= 0x100000;
297 dram_size = fixed_sdram();
300 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
302 * Initialize and enable DDR ECC.
304 ddr_enable_ecc(dram_size);
318 * Initialize Local Bus
324 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
325 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
333 * Fix Local Bus clock glitch when DLL is enabled.
335 * If localbus freq is < 66MHz, DLL bypass mode must be used.
336 * If localbus freq is > 133MHz, DLL can be safely enabled.
337 * Between 66 and 133, the DLL is enabled with an override workaround.
340 get_sys_info(&sysinfo);
341 clkdiv = lbc->lcrr & LCRR_CLKDIV;
342 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
345 lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
347 } else if (lbc_hz >= 133) {
348 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
352 * On REV1 boards, need to change CLKDIV before enable DLL.
353 * Default CLKDIV is 8, change it to 4 temporarily.
355 uint pvr = get_pvr();
356 uint temp_lbcdll = 0;
358 if (pvr == PVR_85xx_REV1) {
359 /* FIXME: Justify the high bit here. */
360 lbc->lcrr = 0x10000004;
363 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
367 * Sample LBC DLL ctrl reg, upshift it to set the
370 temp_lbcdll = gur->lbcdllcr;
371 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
372 asm("sync;isync;msync");
378 * Initialize SDRAM memory on the Local Bus.
384 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
385 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
388 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
391 * Setup SDRAM Base and Option Registers
393 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
394 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
395 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
398 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
399 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
403 * Configure the SDRAM controller.
405 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
408 ppcDcbf((unsigned long) sdram_addr);
411 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
414 ppcDcbf((unsigned long) sdram_addr);
417 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
420 ppcDcbf((unsigned long) sdram_addr);
423 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
426 ppcDcbf((unsigned long) sdram_addr);
429 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
432 ppcDcbf((unsigned long) sdram_addr);
436 #if !defined(CONFIG_SPD_EEPROM)
437 /*************************************************************************
438 * fixed sdram init -- doesn't use serial presence detect.
439 ************************************************************************/
440 long int fixed_sdram (void)
442 #ifndef CONFIG_SYS_RAMBOOT
443 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
445 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
446 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
447 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
448 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
449 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
450 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
451 #if defined (CONFIG_DDR_ECC)
452 ddr->err_disable = 0x0000000D;
453 ddr->err_sbe = 0x00ff0000;
455 asm("sync;isync;msync");
457 #if defined (CONFIG_DDR_ECC)
458 /* Enable ECC checking */
459 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
461 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
463 asm("sync; isync; msync");
466 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
468 #endif /* !defined(CONFIG_SPD_EEPROM) */
471 #if defined(CONFIG_PCI)
473 * Initialize PCI Devices, report devices found.
476 #ifndef CONFIG_PCI_PNP
477 static struct pci_config_table pci_mpc85xxads_config_table[] = {
478 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
479 PCI_IDSEL_NUMBER, PCI_ANY_ID,
480 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
482 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
489 static struct pci_controller hose = {
490 #ifndef CONFIG_PCI_PNP
491 config_table: pci_mpc85xxads_config_table,
495 #endif /* CONFIG_PCI */
502 pci_mpc85xx_init(&hose);
503 #endif /* CONFIG_PCI */
507 #if defined(CONFIG_OF_BOARD_SETUP)
509 ft_board_setup(void *blob, bd_t *bd)
514 ft_cpu_setup(blob, bd);
516 node = fdt_path_offset(blob, "/aliases");
520 path = fdt_getprop(blob, node, "pci0", NULL);
522 tmp[1] = hose.last_busno - hose.first_busno;
523 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);