2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
33 #include <spd_sdram.h>
36 #include <fdt_support.h>
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size);
43 void local_bus_init(void);
44 void sdram_init(void);
45 long int fixed_sdram(void);
49 * I/O Port configuration table
51 * if conf is 1, then that port pin will be configured at boot time
52 * according to the five values podr/pdir/ppar/psor/pdat for that entry
55 const iop_conf_t iop_conf_tab[4][32] = {
57 /* Port A configuration */
58 { /* conf ppar psor pdir podr pdat */
59 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
60 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
61 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
62 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
63 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
64 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
65 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
66 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
67 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
68 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
69 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
70 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
71 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
72 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
73 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
74 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
75 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
76 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
77 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
78 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
79 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
80 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
81 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
82 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
83 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
84 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
85 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
86 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
87 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
88 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
89 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
90 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
93 /* Port B configuration */
94 { /* conf ppar psor pdir podr pdat */
95 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
96 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
97 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
98 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
99 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
100 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
101 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
102 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
103 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
104 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
105 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
106 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
107 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
108 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
109 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
110 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
111 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
112 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
113 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
114 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
115 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
117 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
118 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
119 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
121 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
122 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
123 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
125 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
126 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
130 { /* conf ppar psor pdir podr pdat */
131 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
132 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
133 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
134 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
135 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
136 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
137 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
138 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
139 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
140 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
141 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
142 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
143 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
144 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
145 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
146 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
147 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
148 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
149 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
150 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
151 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
152 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
153 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
154 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
155 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
156 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
157 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
158 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
159 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
160 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
161 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
162 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
166 { /* conf ppar psor pdir podr pdat */
167 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
168 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
169 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
170 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
171 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
172 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
173 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
174 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
175 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
176 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
177 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
178 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
179 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
180 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
181 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
182 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
183 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
184 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
185 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
186 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
187 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
188 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
189 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
190 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
191 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
192 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
193 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
194 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
195 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
196 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
197 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
198 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
204 * MPC8560ADS Board Status & Control Registers
206 typedef struct bcsr_ {
207 volatile unsigned char bcsr0;
208 volatile unsigned char bcsr1;
209 volatile unsigned char bcsr2;
210 volatile unsigned char bcsr3;
211 volatile unsigned char bcsr4;
212 volatile unsigned char bcsr5;
216 int board_early_init_f (void)
221 void reset_phy (void)
223 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
224 volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
226 /* reset Giga bit Ethernet port if needed here */
228 /* reset the CPM FEC port */
229 #if (CONFIG_ETHER_INDEX == 2)
230 bcsr->bcsr2 &= ~FETH2_RST;
232 bcsr->bcsr2 |= FETH2_RST;
234 #elif (CONFIG_ETHER_INDEX == 3)
235 bcsr->bcsr3 &= ~FETH3_RST;
237 bcsr->bcsr3 |= FETH3_RST;
240 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
242 miiphy_reset("FCC1 ETHERNET", 0x0);
244 /* change PHY address to 0x02 */
245 bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
247 bb_miiphy_write(NULL, 0x02, PHY_BMCR,
248 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
249 #endif /* CONFIG_MII */
253 int checkboard (void)
255 puts("Board: ADS\n");
258 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
259 CONFIG_SYS_CLK_FREQ / 1000000);
261 printf(" PCI1: disabled\n");
265 * Initialize local bus.
274 initdram(int board_type)
278 puts("Initializing\n");
280 #if defined(CONFIG_DDR_DLL)
282 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
283 uint temp_ddrdll = 0;
286 * Work around to stabilize DDR DLL
288 temp_ddrdll = gur->ddrdllcr;
289 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
290 asm("sync;isync;msync");
294 #if defined(CONFIG_SPD_EEPROM)
295 dram_size = spd_sdram ();
297 dram_size = fixed_sdram ();
300 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
302 * Initialize and enable DDR ECC.
304 ddr_enable_ecc(dram_size);
318 * Initialize Local Bus
324 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
325 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
333 * Fix Local Bus clock glitch when DLL is enabled.
335 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
336 * If localbus freq is > 133Mhz, DLL can be safely enabled.
337 * Between 66 and 133, the DLL is enabled with an override workaround.
340 get_sys_info(&sysinfo);
341 clkdiv = lbc->lcrr & 0x0f;
342 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
345 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
347 } else if (lbc_hz >= 133) {
348 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
352 * On REV1 boards, need to change CLKDIV before enable DLL.
353 * Default CLKDIV is 8, change it to 4 temporarily.
355 uint pvr = get_pvr();
356 uint temp_lbcdll = 0;
358 if (pvr == PVR_85xx_REV1) {
359 /* FIXME: Justify the high bit here. */
360 lbc->lcrr = 0x10000004;
363 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
367 * Sample LBC DLL ctrl reg, upshift it to set the
370 temp_lbcdll = gur->lbcdllcr;
371 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
372 asm("sync;isync;msync");
378 * Initialize SDRAM memory on the Local Bus.
384 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
385 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
388 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
391 * Setup SDRAM Base and Option Registers
393 lbc->or2 = CFG_OR2_PRELIM;
394 lbc->br2 = CFG_BR2_PRELIM;
395 lbc->lbcr = CFG_LBC_LBCR;
398 lbc->lsrt = CFG_LBC_LSRT;
399 lbc->mrtpr = CFG_LBC_MRTPR;
403 * Configure the SDRAM controller.
405 lbc->lsdmr = CFG_LBC_LSDMR_1;
408 ppcDcbf((unsigned long) sdram_addr);
411 lbc->lsdmr = CFG_LBC_LSDMR_2;
414 ppcDcbf((unsigned long) sdram_addr);
417 lbc->lsdmr = CFG_LBC_LSDMR_3;
420 ppcDcbf((unsigned long) sdram_addr);
423 lbc->lsdmr = CFG_LBC_LSDMR_4;
426 ppcDcbf((unsigned long) sdram_addr);
429 lbc->lsdmr = CFG_LBC_LSDMR_5;
432 ppcDcbf((unsigned long) sdram_addr);
436 #if !defined(CONFIG_SPD_EEPROM)
437 /*************************************************************************
438 * fixed sdram init -- doesn't use serial presence detect.
439 ************************************************************************/
440 long int fixed_sdram (void)
443 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
445 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
446 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
447 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
448 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
449 ddr->sdram_mode = CFG_DDR_MODE;
450 ddr->sdram_interval = CFG_DDR_INTERVAL;
451 #if defined (CONFIG_DDR_ECC)
452 ddr->err_disable = 0x0000000D;
453 ddr->err_sbe = 0x00ff0000;
455 asm("sync;isync;msync");
457 #if defined (CONFIG_DDR_ECC)
458 /* Enable ECC checking */
459 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
461 ddr->sdram_cfg = CFG_DDR_CONTROL;
463 asm("sync; isync; msync");
466 return CFG_SDRAM_SIZE * 1024 * 1024;
468 #endif /* !defined(CONFIG_SPD_EEPROM) */
471 #if defined(CONFIG_PCI)
473 * Initialize PCI Devices, report devices found.
476 #ifndef CONFIG_PCI_PNP
477 static struct pci_config_table pci_mpc85xxads_config_table[] = {
478 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
479 PCI_IDSEL_NUMBER, PCI_ANY_ID,
480 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
482 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
489 static struct pci_controller hose = {
490 #ifndef CONFIG_PCI_PNP
491 config_table: pci_mpc85xxads_config_table,
495 #endif /* CONFIG_PCI */
502 pci_mpc85xx_init(&hose);
503 #endif /* CONFIG_PCI */
507 #if defined(CONFIG_OF_BOARD_SETUP)
509 ft_board_setup(void *blob, bd_t *bd)
514 ft_cpu_setup(blob, bd);
516 node = fdt_path_offset(blob, "/aliases");
520 path = fdt_getprop(blob, node, "pci0", NULL);
522 tmp[1] = hose.last_busno - hose.first_busno;
523 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);