2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
36 #include <fdt_support.h>
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size);
42 extern long int spd_sdram(void);
44 void local_bus_init(void);
45 void sdram_init(void);
46 long int fixed_sdram(void);
50 * I/O Port configuration table
52 * if conf is 1, then that port pin will be configured at boot time
53 * according to the five values podr/pdir/ppar/psor/pdat for that entry
56 const iop_conf_t iop_conf_tab[4][32] = {
58 /* Port A configuration */
59 { /* conf ppar psor pdir podr pdat */
60 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
61 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
62 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
63 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
64 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
65 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
66 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
67 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
68 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
69 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
70 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
71 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
72 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
73 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
74 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
75 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
76 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
77 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
78 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
79 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
80 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
81 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
82 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
83 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
84 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
85 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
86 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
87 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
88 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
89 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
90 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
91 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
94 /* Port B configuration */
95 { /* conf ppar psor pdir podr pdat */
96 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
97 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
98 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
99 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
100 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
101 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
102 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
103 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
104 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
105 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
106 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
107 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
108 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
109 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
110 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
111 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
112 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
113 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
114 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
115 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
116 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
117 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
118 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
119 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
120 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
121 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
122 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
123 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
124 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
125 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
126 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
127 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
131 { /* conf ppar psor pdir podr pdat */
132 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
133 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
134 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
135 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
136 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
137 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
138 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
139 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
140 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
141 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
142 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
143 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
144 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
145 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
146 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
147 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
148 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
149 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
150 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
151 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
152 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
153 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
154 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
155 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
156 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
157 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
158 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
159 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
160 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
161 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
162 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
163 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
167 { /* conf ppar psor pdir podr pdat */
168 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
169 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
170 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
171 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
172 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
173 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
174 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
175 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
176 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
177 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
178 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
179 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
180 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
181 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
182 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
183 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
184 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
185 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
186 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
187 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
188 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
189 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
190 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
191 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
192 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
193 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
194 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
195 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
196 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
197 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
198 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
199 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
205 * MPC8560ADS Board Status & Control Registers
207 typedef struct bcsr_ {
208 volatile unsigned char bcsr0;
209 volatile unsigned char bcsr1;
210 volatile unsigned char bcsr2;
211 volatile unsigned char bcsr3;
212 volatile unsigned char bcsr4;
213 volatile unsigned char bcsr5;
217 int board_early_init_f (void)
222 void reset_phy (void)
224 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
225 volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
227 /* reset Giga bit Ethernet port if needed here */
229 /* reset the CPM FEC port */
230 #if (CONFIG_ETHER_INDEX == 2)
231 bcsr->bcsr2 &= ~FETH2_RST;
233 bcsr->bcsr2 |= FETH2_RST;
235 #elif (CONFIG_ETHER_INDEX == 3)
236 bcsr->bcsr3 &= ~FETH3_RST;
238 bcsr->bcsr3 |= FETH3_RST;
241 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
243 miiphy_reset("FCC1 ETHERNET", 0x0);
245 /* change PHY address to 0x02 */
246 bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
248 bb_miiphy_write(NULL, 0x02, PHY_BMCR,
249 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
250 #endif /* CONFIG_MII */
254 int checkboard (void)
256 puts("Board: ADS\n");
259 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
260 CONFIG_SYS_CLK_FREQ / 1000000);
262 printf(" PCI1: disabled\n");
266 * Initialize local bus.
275 initdram(int board_type)
278 extern long spd_sdram (void);
280 puts("Initializing\n");
282 #if defined(CONFIG_DDR_DLL)
284 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
285 uint temp_ddrdll = 0;
288 * Work around to stabilize DDR DLL
290 temp_ddrdll = gur->ddrdllcr;
291 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
292 asm("sync;isync;msync");
296 #if defined(CONFIG_SPD_EEPROM)
297 dram_size = spd_sdram ();
299 dram_size = fixed_sdram ();
302 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
304 * Initialize and enable DDR ECC.
306 ddr_enable_ecc(dram_size);
320 * Initialize Local Bus
326 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
327 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
335 * Fix Local Bus clock glitch when DLL is enabled.
337 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
338 * If localbus freq is > 133Mhz, DLL can be safely enabled.
339 * Between 66 and 133, the DLL is enabled with an override workaround.
342 get_sys_info(&sysinfo);
343 clkdiv = lbc->lcrr & 0x0f;
344 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
347 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
349 } else if (lbc_hz >= 133) {
350 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
354 * On REV1 boards, need to change CLKDIV before enable DLL.
355 * Default CLKDIV is 8, change it to 4 temporarily.
357 uint pvr = get_pvr();
358 uint temp_lbcdll = 0;
360 if (pvr == PVR_85xx_REV1) {
361 /* FIXME: Justify the high bit here. */
362 lbc->lcrr = 0x10000004;
365 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
369 * Sample LBC DLL ctrl reg, upshift it to set the
372 temp_lbcdll = gur->lbcdllcr;
373 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
374 asm("sync;isync;msync");
380 * Initialize SDRAM memory on the Local Bus.
386 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
387 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
390 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
393 * Setup SDRAM Base and Option Registers
395 lbc->or2 = CFG_OR2_PRELIM;
396 lbc->br2 = CFG_BR2_PRELIM;
397 lbc->lbcr = CFG_LBC_LBCR;
400 lbc->lsrt = CFG_LBC_LSRT;
401 lbc->mrtpr = CFG_LBC_MRTPR;
405 * Configure the SDRAM controller.
407 lbc->lsdmr = CFG_LBC_LSDMR_1;
410 ppcDcbf((unsigned long) sdram_addr);
413 lbc->lsdmr = CFG_LBC_LSDMR_2;
416 ppcDcbf((unsigned long) sdram_addr);
419 lbc->lsdmr = CFG_LBC_LSDMR_3;
422 ppcDcbf((unsigned long) sdram_addr);
425 lbc->lsdmr = CFG_LBC_LSDMR_4;
428 ppcDcbf((unsigned long) sdram_addr);
431 lbc->lsdmr = CFG_LBC_LSDMR_5;
434 ppcDcbf((unsigned long) sdram_addr);
439 #if defined(CFG_DRAM_TEST)
442 uint *pstart = (uint *) CFG_MEMTEST_START;
443 uint *pend = (uint *) CFG_MEMTEST_END;
446 printf("SDRAM test phase 1:\n");
447 for (p = pstart; p < pend; p++)
450 for (p = pstart; p < pend; p++) {
451 if (*p != 0xaaaaaaaa) {
452 printf ("SDRAM test fails at: %08x\n", (uint) p);
457 printf("SDRAM test phase 2:\n");
458 for (p = pstart; p < pend; p++)
461 for (p = pstart; p < pend; p++) {
462 if (*p != 0x55555555) {
463 printf ("SDRAM test fails at: %08x\n", (uint) p);
468 printf("SDRAM test passed.\n");
474 #if !defined(CONFIG_SPD_EEPROM)
475 /*************************************************************************
476 * fixed sdram init -- doesn't use serial presence detect.
477 ************************************************************************/
478 long int fixed_sdram (void)
481 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
483 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
484 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
485 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
486 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
487 ddr->sdram_mode = CFG_DDR_MODE;
488 ddr->sdram_interval = CFG_DDR_INTERVAL;
489 #if defined (CONFIG_DDR_ECC)
490 ddr->err_disable = 0x0000000D;
491 ddr->err_sbe = 0x00ff0000;
493 asm("sync;isync;msync");
495 #if defined (CONFIG_DDR_ECC)
496 /* Enable ECC checking */
497 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
499 ddr->sdram_cfg = CFG_DDR_CONTROL;
501 asm("sync; isync; msync");
504 return CFG_SDRAM_SIZE * 1024 * 1024;
506 #endif /* !defined(CONFIG_SPD_EEPROM) */
509 #if defined(CONFIG_PCI)
511 * Initialize PCI Devices, report devices found.
514 #ifndef CONFIG_PCI_PNP
515 static struct pci_config_table pci_mpc85xxads_config_table[] = {
516 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
517 PCI_IDSEL_NUMBER, PCI_ANY_ID,
518 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
520 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
527 static struct pci_controller hose = {
528 #ifndef CONFIG_PCI_PNP
529 config_table: pci_mpc85xxads_config_table,
533 #endif /* CONFIG_PCI */
540 pci_mpc85xx_init(&hose);
541 #endif /* CONFIG_PCI */
545 #if defined(CONFIG_OF_BOARD_SETUP)
547 ft_board_setup(void *blob, bd_t *bd)
552 ft_cpu_setup(blob, bd);
554 node = fdt_path_offset(blob, "/aliases");
558 path = fdt_getprop(blob, node, "pci0", NULL);
560 tmp[1] = hose.last_busno - hose.first_busno;
561 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);