2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
41 long int fixed_sdram(void);
45 puts ("Board: MPC8572DS ");
46 #ifdef CONFIG_PHYS_64BIT
47 puts ("(36-bit addrmap) ");
49 printf ("Sys ID: 0x%02x, "
50 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
51 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
52 in8(PIXIS_BASE + PIXIS_PVER));
56 phys_size_t initdram(int board_type)
58 phys_size_t dram_size = 0;
60 puts("Initializing....");
62 #ifdef CONFIG_SPD_EEPROM
63 dram_size = fsl_ddr_sdram();
65 dram_size = fixed_sdram();
67 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
68 dram_size *= 0x100000;
74 #if !defined(CONFIG_SPD_EEPROM)
76 * Fixed sdram init -- doesn't use serial presence detect.
79 phys_size_t fixed_sdram (void)
81 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
82 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
85 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
86 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
88 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
89 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
90 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
91 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
92 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
93 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
94 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
95 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
96 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
97 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
99 #if defined (CONFIG_DDR_ECC)
100 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
101 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
102 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
108 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
110 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
112 debug("DDR - 1st controller: memory initializing\n");
114 * Poll until memory is initialized.
115 * 512 Meg at 400 might hit this 200 times or so.
117 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
120 debug("DDR: memory initialized\n\n");
125 return 512 * 1024 * 1024;
131 static struct pci_controller pcie1_hose;
135 static struct pci_controller pcie2_hose;
139 static struct pci_controller pcie3_hose;
142 int first_free_busno=0;
144 void pci_init_board(void)
146 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
147 uint devdisr = gur->devdisr;
148 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
149 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
151 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
152 devdisr, io_sel, host_agent);
154 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
155 printf (" eTSEC1 is in sgmii mode.\n");
156 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
157 printf (" eTSEC2 is in sgmii mode.\n");
158 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
159 printf (" eTSEC3 is in sgmii mode.\n");
160 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
161 printf (" eTSEC4 is in sgmii mode.\n");
166 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
167 struct pci_controller *hose = &pcie3_hose;
168 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
169 (host_agent == 5) || (host_agent == 6);
170 int pcie_configured = (io_sel == 0x7);
171 struct pci_region *r = hose->regions;
174 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
175 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
176 pcie_ep ? "End Point" : "Root Complex",
178 if (pci->pme_msg_det) {
179 pci->pme_msg_det = 0xffffffff;
180 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
185 r += fsl_pci_setup_inbound_windows(r);
187 /* outbound memory */
189 CONFIG_SYS_PCIE3_MEM_BUS,
190 CONFIG_SYS_PCIE3_MEM_PHYS,
191 CONFIG_SYS_PCIE3_MEM_SIZE,
196 CONFIG_SYS_PCIE3_IO_BUS,
197 CONFIG_SYS_PCIE3_IO_PHYS,
198 CONFIG_SYS_PCIE3_IO_SIZE,
201 hose->region_count = r - hose->regions;
202 hose->first_busno=first_free_busno;
203 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
207 first_free_busno=hose->last_busno+1;
208 printf (" PCIE3 on bus %02x - %02x\n",
209 hose->first_busno,hose->last_busno);
212 * Activate ULI1575 legacy chip by performing a fake
213 * memory access. Needed to make ULI RTC work.
214 * Device 1d has the first on-board memory BAR.
217 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
218 PCI_BASE_ADDRESS_1, &temp32);
219 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
220 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
222 debug(" uli1572 read to %p\n", p);
226 printf (" PCIE3: disabled\n");
231 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
236 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
237 struct pci_controller *hose = &pcie2_hose;
238 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
239 (host_agent == 6) || (host_agent == 0);
240 int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
241 struct pci_region *r = hose->regions;
243 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
244 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
245 pcie_ep ? "End Point" : "Root Complex",
247 if (pci->pme_msg_det) {
248 pci->pme_msg_det = 0xffffffff;
249 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
254 r += fsl_pci_setup_inbound_windows(r);
256 /* outbound memory */
258 CONFIG_SYS_PCIE2_MEM_BUS,
259 CONFIG_SYS_PCIE2_MEM_PHYS,
260 CONFIG_SYS_PCIE2_MEM_SIZE,
265 CONFIG_SYS_PCIE2_IO_BUS,
266 CONFIG_SYS_PCIE2_IO_PHYS,
267 CONFIG_SYS_PCIE2_IO_SIZE,
270 hose->region_count = r - hose->regions;
271 hose->first_busno=first_free_busno;
272 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
275 first_free_busno=hose->last_busno+1;
276 printf (" PCIE2 on bus %02x - %02x\n",
277 hose->first_busno,hose->last_busno);
280 printf (" PCIE2: disabled\n");
285 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
289 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
290 struct pci_controller *hose = &pcie1_hose;
291 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
293 int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
294 (io_sel == 0x7) || (io_sel == 0xb) ||
295 (io_sel == 0xc) || (io_sel == 0xf);
296 struct pci_region *r = hose->regions;
298 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
299 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
300 pcie_ep ? "End Point" : "Root Complex",
302 if (pci->pme_msg_det) {
303 pci->pme_msg_det = 0xffffffff;
304 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
309 r += fsl_pci_setup_inbound_windows(r);
311 /* outbound memory */
313 CONFIG_SYS_PCIE1_MEM_BUS,
314 CONFIG_SYS_PCIE1_MEM_PHYS,
315 CONFIG_SYS_PCIE1_MEM_SIZE,
320 CONFIG_SYS_PCIE1_IO_BUS,
321 CONFIG_SYS_PCIE1_IO_PHYS,
322 CONFIG_SYS_PCIE1_IO_SIZE,
325 hose->region_count = r - hose->regions;
326 hose->first_busno=first_free_busno;
328 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
332 first_free_busno=hose->last_busno+1;
333 printf(" PCIE1 on bus %02x - %02x\n",
334 hose->first_busno,hose->last_busno);
337 printf (" PCIE1: disabled\n");
342 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
347 int board_early_init_r(void)
349 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
350 const u8 flash_esel = 2;
353 * Remap Boot flash + PROMJET region to caching-inhibited
354 * so that flash can be erased properly.
357 /* Flush d-cache and invalidate i-cache of any FLASH data */
361 /* invalidate existing TLB entry for flash + promjet */
362 disable_tlb(flash_esel);
364 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
365 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
366 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
371 #ifdef CONFIG_GET_CLK_FROM_ICS307
372 /* decode S[0-2] to Output Divider (OD) */
373 static unsigned char ics307_S_to_OD[] = {
374 10, 2, 8, 4, 5, 7, 3, 6
377 /* Calculate frequency being generated by ICS307-02 clock chip based upon
378 * the control bytes being programmed into it. */
379 /* XXX: This function should probably go into a common library */
381 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
383 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
384 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
385 unsigned long RDW = cw2 & 0x7F;
386 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
389 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
391 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
392 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
393 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
395 * R6:R0 = Reference Divider Word (RDW)
396 * V8:V0 = VCO Divider Word (VDW)
397 * S2:S0 = Output Divider Select (OD)
398 * F1:F0 = Function of CLK2 Output
400 * C1:C0 = internal load capacitance for cyrstal
403 /* Adding 1 to get a "nicely" rounded number, but this needs
404 * more tweaking to get a "properly" rounded number. */
406 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
408 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
413 unsigned long get_board_sys_clk(ulong dummy)
415 return ics307_clk_freq (
416 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
417 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
418 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
422 unsigned long get_board_ddr_clk(ulong dummy)
424 return ics307_clk_freq (
425 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
426 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
427 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
431 unsigned long get_board_sys_clk(ulong dummy)
436 i = in8(PIXIS_BASE + PIXIS_SPD);
469 unsigned long get_board_ddr_clk(ulong dummy)
474 i = in8(PIXIS_BASE + PIXIS_SPD);
508 #ifdef CONFIG_TSEC_ENET
509 int board_eth_init(bd_t *bis)
511 struct tsec_info_struct tsec_info[4];
512 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
516 SET_STD_TSEC_INFO(tsec_info[num], 1);
517 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
518 tsec_info[num].flags |= TSEC_SGMII;
522 SET_STD_TSEC_INFO(tsec_info[num], 2);
523 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
524 tsec_info[num].flags |= TSEC_SGMII;
528 SET_STD_TSEC_INFO(tsec_info[num], 3);
529 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
530 tsec_info[num].flags |= TSEC_SGMII;
534 SET_STD_TSEC_INFO(tsec_info[num], 4);
535 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
536 tsec_info[num].flags |= TSEC_SGMII;
541 printf("No TSECs initialized\n");
546 #ifdef CONFIG_FSL_SGMII_RISER
547 fsl_sgmii_riser_init(tsec_info, num);
550 tsec_eth_init(bis, tsec_info, num);
556 #if defined(CONFIG_OF_BOARD_SETUP)
557 void ft_board_setup(void *blob, bd_t *bd)
562 ft_cpu_setup(blob, bd);
564 base = getenv_bootm_low();
565 size = getenv_bootm_size();
567 fdt_fixup_memory(blob, (u64)base, (u64)size);
570 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
573 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
576 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
578 #ifdef CONFIG_FSL_SGMII_RISER
579 fsl_sgmii_riser_fdt_fixup(blob);
585 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
587 void board_lmb_reserve(struct lmb *lmb)
589 cpu_mp_lmb_reserve(lmb);