2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
39 #include "../common/pixis.h"
40 #include "../common/sgmii_riser.h"
42 long int fixed_sdram(void);
47 u8 *pixis_base = (u8 *)PIXIS_BASE;
49 puts ("Board: MPC8572DS ");
50 #ifdef CONFIG_PHYS_64BIT
51 puts ("(36-bit addrmap) ");
53 printf ("Sys ID: 0x%02x, "
54 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
55 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
56 in_8(pixis_base + PIXIS_PVER));
58 vboot = in_8(pixis_base + PIXIS_VBOOT);
59 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
60 case PIXIS_VBOOT_LBMAP_NOR0:
63 case PIXIS_VBOOT_LBMAP_PJET:
66 case PIXIS_VBOOT_LBMAP_NAND:
69 case PIXIS_VBOOT_LBMAP_NOR1:
77 phys_size_t initdram(int board_type)
79 phys_size_t dram_size = 0;
81 puts("Initializing....");
83 #ifdef CONFIG_SPD_EEPROM
84 dram_size = fsl_ddr_sdram();
86 dram_size = fixed_sdram();
88 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
89 dram_size *= 0x100000;
95 #if !defined(CONFIG_SPD_EEPROM)
97 * Fixed sdram init -- doesn't use serial presence detect.
100 phys_size_t fixed_sdram (void)
102 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
103 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
106 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
107 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
109 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
110 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
111 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
112 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
113 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
114 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
115 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
116 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
117 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
118 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
120 #if defined (CONFIG_DDR_ECC)
121 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
122 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
123 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
129 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
131 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
133 debug("DDR - 1st controller: memory initializing\n");
135 * Poll until memory is initialized.
136 * 512 Meg at 400 might hit this 200 times or so.
138 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
141 debug("DDR: memory initialized\n\n");
146 return 512 * 1024 * 1024;
152 static struct pci_controller pcie1_hose;
156 static struct pci_controller pcie2_hose;
160 static struct pci_controller pcie3_hose;
163 int first_free_busno=0;
165 void pci_init_board(void)
167 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
168 uint devdisr = gur->devdisr;
169 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
170 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
172 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
173 devdisr, io_sel, host_agent);
175 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
176 printf (" eTSEC1 is in sgmii mode.\n");
177 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
178 printf (" eTSEC2 is in sgmii mode.\n");
179 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
180 printf (" eTSEC3 is in sgmii mode.\n");
181 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
182 printf (" eTSEC4 is in sgmii mode.\n");
187 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
188 struct pci_controller *hose = &pcie3_hose;
189 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
190 (host_agent == 5) || (host_agent == 6);
191 int pcie_configured = (io_sel == 0x7);
192 struct pci_region *r = hose->regions;
195 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
196 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
197 pcie_ep ? "End Point" : "Root Complex",
199 if (pci->pme_msg_det) {
200 pci->pme_msg_det = 0xffffffff;
201 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
205 /* outbound memory */
207 CONFIG_SYS_PCIE3_MEM_BUS,
208 CONFIG_SYS_PCIE3_MEM_PHYS,
209 CONFIG_SYS_PCIE3_MEM_SIZE,
214 CONFIG_SYS_PCIE3_IO_BUS,
215 CONFIG_SYS_PCIE3_IO_PHYS,
216 CONFIG_SYS_PCIE3_IO_SIZE,
219 hose->region_count = r - hose->regions;
220 hose->first_busno=first_free_busno;
222 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
224 first_free_busno=hose->last_busno+1;
225 printf (" PCIE3 on bus %02x - %02x\n",
226 hose->first_busno,hose->last_busno);
229 * Activate ULI1575 legacy chip by performing a fake
230 * memory access. Needed to make ULI RTC work.
231 * Device 1d has the first on-board memory BAR.
234 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
235 PCI_BASE_ADDRESS_1, &temp32);
236 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
237 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
239 debug(" uli1572 read to %p\n", p);
243 printf (" PCIE3: disabled\n");
248 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
253 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
254 struct pci_controller *hose = &pcie2_hose;
255 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
256 (host_agent == 6) || (host_agent == 0);
257 int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
258 struct pci_region *r = hose->regions;
260 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
261 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
262 pcie_ep ? "End Point" : "Root Complex",
264 if (pci->pme_msg_det) {
265 pci->pme_msg_det = 0xffffffff;
266 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
270 /* outbound memory */
272 CONFIG_SYS_PCIE2_MEM_BUS,
273 CONFIG_SYS_PCIE2_MEM_PHYS,
274 CONFIG_SYS_PCIE2_MEM_SIZE,
279 CONFIG_SYS_PCIE2_IO_BUS,
280 CONFIG_SYS_PCIE2_IO_PHYS,
281 CONFIG_SYS_PCIE2_IO_SIZE,
284 hose->region_count = r - hose->regions;
285 hose->first_busno=first_free_busno;
287 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
288 first_free_busno=hose->last_busno+1;
289 printf (" PCIE2 on bus %02x - %02x\n",
290 hose->first_busno,hose->last_busno);
293 printf (" PCIE2: disabled\n");
298 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
302 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
303 struct pci_controller *hose = &pcie1_hose;
304 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
306 int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
307 (io_sel == 0x7) || (io_sel == 0xb) ||
308 (io_sel == 0xc) || (io_sel == 0xf);
309 struct pci_region *r = hose->regions;
311 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
312 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
313 pcie_ep ? "End Point" : "Root Complex",
315 if (pci->pme_msg_det) {
316 pci->pme_msg_det = 0xffffffff;
317 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
321 /* outbound memory */
323 CONFIG_SYS_PCIE1_MEM_BUS,
324 CONFIG_SYS_PCIE1_MEM_PHYS,
325 CONFIG_SYS_PCIE1_MEM_SIZE,
330 CONFIG_SYS_PCIE1_IO_BUS,
331 CONFIG_SYS_PCIE1_IO_PHYS,
332 CONFIG_SYS_PCIE1_IO_SIZE,
335 hose->region_count = r - hose->regions;
336 hose->first_busno=first_free_busno;
338 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
340 first_free_busno=hose->last_busno+1;
341 printf(" PCIE1 on bus %02x - %02x\n",
342 hose->first_busno,hose->last_busno);
345 printf (" PCIE1: disabled\n");
350 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
355 int board_early_init_r(void)
357 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
358 const u8 flash_esel = 2;
361 * Remap Boot flash + PROMJET region to caching-inhibited
362 * so that flash can be erased properly.
365 /* Flush d-cache and invalidate i-cache of any FLASH data */
369 /* invalidate existing TLB entry for flash + promjet */
370 disable_tlb(flash_esel);
372 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
373 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
374 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
379 #ifdef CONFIG_GET_CLK_FROM_ICS307
380 /* decode S[0-2] to Output Divider (OD) */
381 static unsigned char ics307_S_to_OD[] = {
382 10, 2, 8, 4, 5, 7, 3, 6
385 /* Calculate frequency being generated by ICS307-02 clock chip based upon
386 * the control bytes being programmed into it. */
387 /* XXX: This function should probably go into a common library */
389 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
391 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
392 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
393 unsigned long RDW = cw2 & 0x7F;
394 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
397 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
399 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
400 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
401 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
403 * R6:R0 = Reference Divider Word (RDW)
404 * V8:V0 = VCO Divider Word (VDW)
405 * S2:S0 = Output Divider Select (OD)
406 * F1:F0 = Function of CLK2 Output
408 * C1:C0 = internal load capacitance for cyrstal
411 /* Adding 1 to get a "nicely" rounded number, but this needs
412 * more tweaking to get a "properly" rounded number. */
414 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
416 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
421 unsigned long get_board_sys_clk(ulong dummy)
423 u8 *pixis_base = (u8 *)PIXIS_BASE;
425 return ics307_clk_freq (
426 in_8(pixis_base + PIXIS_VSYSCLK0),
427 in_8(pixis_base + PIXIS_VSYSCLK1),
428 in_8(pixis_base + PIXIS_VSYSCLK2)
432 unsigned long get_board_ddr_clk(ulong dummy)
434 u8 *pixis_base = (u8 *)PIXIS_BASE;
436 return ics307_clk_freq (
437 in_8(pixis_base + PIXIS_VDDRCLK0),
438 in_8(pixis_base + PIXIS_VDDRCLK1),
439 in_8(pixis_base + PIXIS_VDDRCLK2)
443 unsigned long get_board_sys_clk(ulong dummy)
447 u8 *pixis_base = (u8 *)PIXIS_BASE;
449 i = in_8(pixis_base + PIXIS_SPD);
482 unsigned long get_board_ddr_clk(ulong dummy)
486 u8 *pixis_base = (u8 *)PIXIS_BASE;
488 i = in_8(pixis_base + PIXIS_SPD);
522 #ifdef CONFIG_TSEC_ENET
523 int board_eth_init(bd_t *bis)
525 struct tsec_info_struct tsec_info[4];
526 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
530 SET_STD_TSEC_INFO(tsec_info[num], 1);
531 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
532 tsec_info[num].flags |= TSEC_SGMII;
536 SET_STD_TSEC_INFO(tsec_info[num], 2);
537 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
538 tsec_info[num].flags |= TSEC_SGMII;
542 SET_STD_TSEC_INFO(tsec_info[num], 3);
543 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
544 tsec_info[num].flags |= TSEC_SGMII;
548 SET_STD_TSEC_INFO(tsec_info[num], 4);
549 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
550 tsec_info[num].flags |= TSEC_SGMII;
555 printf("No TSECs initialized\n");
560 #ifdef CONFIG_FSL_SGMII_RISER
561 fsl_sgmii_riser_init(tsec_info, num);
564 tsec_eth_init(bis, tsec_info, num);
566 return pci_eth_init(bis);
570 #if defined(CONFIG_OF_BOARD_SETUP)
571 void ft_board_setup(void *blob, bd_t *bd)
576 ft_cpu_setup(blob, bd);
578 base = getenv_bootm_low();
579 size = getenv_bootm_size();
581 fdt_fixup_memory(blob, (u64)base, (u64)size);
584 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
587 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
590 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
592 #ifdef CONFIG_FSL_SGMII_RISER
593 fsl_sgmii_riser_fdt_fixup(blob);
599 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
601 void board_lmb_reserve(struct lmb *lmb)
603 cpu_mp_lmb_reserve(lmb);