git.sur5r.net Git - u-boot/blob - board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <netdev.h>
  38
  39 #include "../common/pixis.h"
  40 #include "../common/sgmii_riser.h"
  41
  42 long int fixed_sdram(void);
  43
  44 int checkboard (void)
  45 {
  46         u8 vboot;
  47         u8 *pixis_base = (u8 *)PIXIS_BASE;
  48
  49         puts ("Board: MPC8572DS ");
  50 #ifdef CONFIG_PHYS_64BIT
  51         puts ("(36-bit addrmap) ");
  52 #endif
  53         printf ("Sys ID: 0x%02x, "
  54                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  55                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  56                 in_8(pixis_base + PIXIS_PVER));
  57
  58         vboot = in_8(pixis_base + PIXIS_VBOOT);
  59         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
  60                 case PIXIS_VBOOT_LBMAP_NOR0:
  61                         puts ("vBank: 0\n");
  62                         break;
  63                 case PIXIS_VBOOT_LBMAP_PJET:
  64                         puts ("Promjet\n");
  65                         break;
  66                 case PIXIS_VBOOT_LBMAP_NAND:
  67                         puts ("NAND\n");
  68                         break;
  69                 case PIXIS_VBOOT_LBMAP_NOR1:
  70                         puts ("vBank: 1\n");
  71                         break;
  72         }
  73
  74         return 0;
  75 }
  76
  77 phys_size_t initdram(int board_type)
  78 {
  79         phys_size_t dram_size = 0;
  80
  81         puts("Initializing....");
  82
  83 #ifdef CONFIG_SPD_EEPROM
  84         dram_size = fsl_ddr_sdram();
  85 #else
  86         dram_size = fixed_sdram();
  87 #endif
  88         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  89         dram_size *= 0x100000;
  90
  91         puts("    DDR: ");
  92         return dram_size;
  93 }
  94
  95 #if !defined(CONFIG_SPD_EEPROM)
  96 /*
  97  * Fixed sdram init -- doesn't use serial presence detect.
  98  */
  99
 100 phys_size_t fixed_sdram (void)
 101 {
 102         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 103         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 104         uint d_init;
 105
 106         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 107         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 108
 109         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 110         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 111         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 112         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 113         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 114         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 115         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 116         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 117         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 118         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 119
 120 #if defined (CONFIG_DDR_ECC)
 121         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 122         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 123         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 124 #endif
 125         asm("sync;isync");
 126
 127         udelay(500);
 128
 129         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 130
 131 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 132         d_init = 1;
 133         debug("DDR - 1st controller: memory initializing\n");
 134         /*
 135          * Poll until memory is initialized.
 136          * 512 Meg at 400 might hit this 200 times or so.
 137          */
 138         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 139                 udelay(1000);
 140         }
 141         debug("DDR: memory initialized\n\n");
 142         asm("sync; isync");
 143         udelay(500);
 144 #endif
 145
 146         return 512 * 1024 * 1024;
 147 }
 148
 149 #endif
 150
 151 #ifdef CONFIG_PCIE1
 152 static struct pci_controller pcie1_hose;
 153 #endif
 154
 155 #ifdef CONFIG_PCIE2
 156 static struct pci_controller pcie2_hose;
 157 #endif
 158
 159 #ifdef CONFIG_PCIE3
 160 static struct pci_controller pcie3_hose;
 161 #endif
 162
 163 int first_free_busno=0;
 164 #ifdef CONFIG_PCI
 165 void pci_init_board(void)
 166 {
 167         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 168         uint devdisr = gur->devdisr;
 169         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 170         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 171
 172         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 173                         devdisr, io_sel, host_agent);
 174
 175         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 176                 printf ("    eTSEC1 is in sgmii mode.\n");
 177         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 178                 printf ("    eTSEC2 is in sgmii mode.\n");
 179         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 180                 printf ("    eTSEC3 is in sgmii mode.\n");
 181         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 182                 printf ("    eTSEC4 is in sgmii mode.\n");
 183
 184
 185 #ifdef CONFIG_PCIE3
 186         {
 187                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 188                 struct pci_controller *hose = &pcie3_hose;
 189                 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 190                         (host_agent == 5) || (host_agent == 6);
 191                 int pcie_configured  = (io_sel == 0x7);
 192                 struct pci_region *r = hose->regions;
 193                 u32 temp32;
 194
 195                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 196                         printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 197                                         pcie_ep ? "End Point" : "Root Complex",
 198                                         (uint)pci);
 199                         if (pci->pme_msg_det) {
 200                                 pci->pme_msg_det = 0xffffffff;
 201                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 202                         }
 203                         printf ("\n");
 204
 205                         /* outbound memory */
 206                         pci_set_region(r++,
 207                                         CONFIG_SYS_PCIE3_MEM_BUS,
 208                                         CONFIG_SYS_PCIE3_MEM_PHYS,
 209                                         CONFIG_SYS_PCIE3_MEM_SIZE,
 210                                         PCI_REGION_MEM);
 211
 212                         /* outbound io */
 213                         pci_set_region(r++,
 214                                         CONFIG_SYS_PCIE3_IO_BUS,
 215                                         CONFIG_SYS_PCIE3_IO_PHYS,
 216                                         CONFIG_SYS_PCIE3_IO_SIZE,
 217                                         PCI_REGION_IO);
 218
 219                         hose->region_count = r - hose->regions;
 220                         hose->first_busno=first_free_busno;
 221
 222                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 223
 224                         first_free_busno=hose->last_busno+1;
 225                         printf ("    PCIE3 on bus %02x - %02x\n",
 226                                         hose->first_busno,hose->last_busno);
 227
 228                         /*
 229                          * Activate ULI1575 legacy chip by performing a fake
 230                          * memory access.  Needed to make ULI RTC work.
 231                          * Device 1d has the first on-board memory BAR.
 232                          */
 233
 234                         pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 235                                         PCI_BASE_ADDRESS_1, &temp32);
 236                         if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 237                                 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 238                                                                 temp32, 4, 0);
 239                                 debug(" uli1572 read to %p\n", p);
 240                                 in_be32(p);
 241                         }
 242                 } else {
 243                         printf ("    PCIE3: disabled\n");
 244                 }
 245
 246         }
 247 #else
 248         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 249 #endif
 250
 251 #ifdef CONFIG_PCIE2
 252         {
 253                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 254                 struct pci_controller *hose = &pcie2_hose;
 255                 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 256                         (host_agent == 6) || (host_agent == 0);
 257                 int pcie_configured  = (io_sel == 0x3) || (io_sel == 0x7);
 258                 struct pci_region *r = hose->regions;
 259
 260                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 261                         printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 262                                         pcie_ep ? "End Point" : "Root Complex",
 263                                         (uint)pci);
 264                         if (pci->pme_msg_det) {
 265                                 pci->pme_msg_det = 0xffffffff;
 266                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 267                         }
 268                         printf ("\n");
 269
 270                         /* outbound memory */
 271                         pci_set_region(r++,
 272                                         CONFIG_SYS_PCIE2_MEM_BUS,
 273                                         CONFIG_SYS_PCIE2_MEM_PHYS,
 274                                         CONFIG_SYS_PCIE2_MEM_SIZE,
 275                                         PCI_REGION_MEM);
 276
 277                         /* outbound io */
 278                         pci_set_region(r++,
 279                                         CONFIG_SYS_PCIE2_IO_BUS,
 280                                         CONFIG_SYS_PCIE2_IO_PHYS,
 281                                         CONFIG_SYS_PCIE2_IO_SIZE,
 282                                         PCI_REGION_IO);
 283
 284                         hose->region_count = r - hose->regions;
 285                         hose->first_busno=first_free_busno;
 286
 287                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 288                         first_free_busno=hose->last_busno+1;
 289                         printf ("    PCIE2 on bus %02x - %02x\n",
 290                                         hose->first_busno,hose->last_busno);
 291
 292                 } else {
 293                         printf ("    PCIE2: disabled\n");
 294                 }
 295
 296         }
 297 #else
 298         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 299 #endif
 300 #ifdef CONFIG_PCIE1
 301         {
 302                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 303                 struct pci_controller *hose = &pcie1_hose;
 304                 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 305                         (host_agent == 5);
 306                 int pcie_configured  = (io_sel == 0x2) || (io_sel == 0x3) ||
 307                                         (io_sel == 0x7) || (io_sel == 0xb) ||
 308                                         (io_sel == 0xc) || (io_sel == 0xf);
 309                 struct pci_region *r = hose->regions;
 310
 311                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 312                         printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
 313                                         pcie_ep ? "End Point" : "Root Complex",
 314                                         (uint)pci);
 315                         if (pci->pme_msg_det) {
 316                                 pci->pme_msg_det = 0xffffffff;
 317                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 318                         }
 319                         printf ("\n");
 320
 321                         /* outbound memory */
 322                         pci_set_region(r++,
 323                                         CONFIG_SYS_PCIE1_MEM_BUS,
 324                                         CONFIG_SYS_PCIE1_MEM_PHYS,
 325                                         CONFIG_SYS_PCIE1_MEM_SIZE,
 326                                         PCI_REGION_MEM);
 327
 328                         /* outbound io */
 329                         pci_set_region(r++,
 330                                         CONFIG_SYS_PCIE1_IO_BUS,
 331                                         CONFIG_SYS_PCIE1_IO_PHYS,
 332                                         CONFIG_SYS_PCIE1_IO_SIZE,
 333                                         PCI_REGION_IO);
 334
 335                         hose->region_count = r - hose->regions;
 336                         hose->first_busno=first_free_busno;
 337
 338                         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 339
 340                         first_free_busno=hose->last_busno+1;
 341                         printf("    PCIE1 on bus %02x - %02x\n",
 342                                         hose->first_busno,hose->last_busno);
 343
 344                 } else {
 345                         printf ("    PCIE1: disabled\n");
 346                 }
 347
 348         }
 349 #else
 350         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 351 #endif
 352 }
 353 #endif
 354
 355 int board_early_init_r(void)
 356 {
 357         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 358         const u8 flash_esel = 2;
 359
 360         /*
 361          * Remap Boot flash + PROMJET region to caching-inhibited
 362          * so that flash can be erased properly.
 363          */
 364
 365         /* Flush d-cache and invalidate i-cache of any FLASH data */
 366         flush_dcache();
 367         invalidate_icache();
 368
 369         /* invalidate existing TLB entry for flash + promjet */
 370         disable_tlb(flash_esel);
 371
 372         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 373                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 374                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 375
 376         return 0;
 377 }
 378
 379 #ifdef CONFIG_GET_CLK_FROM_ICS307
 380 /* decode S[0-2] to Output Divider (OD) */
 381 static unsigned char ics307_S_to_OD[] = {
 382         10, 2, 8, 4, 5, 7, 3, 6
 383 };
 384
 385 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 386  * the control bytes being programmed into it. */
 387 /* XXX: This function should probably go into a common library */
 388 static unsigned long
 389 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 390 {
 391         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 392         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 393         unsigned long RDW = cw2 & 0x7F;
 394         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 395         unsigned long freq;
 396
 397         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 398
 399         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 400          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 401          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 402          *
 403          * R6:R0 = Reference Divider Word (RDW)
 404          * V8:V0 = VCO Divider Word (VDW)
 405          * S2:S0 = Output Divider Select (OD)
 406          * F1:F0 = Function of CLK2 Output
 407          * TTL = duty cycle
 408          * C1:C0 = internal load capacitance for cyrstal
 409          */
 410
 411         /* Adding 1 to get a "nicely" rounded number, but this needs
 412          * more tweaking to get a "properly" rounded number. */
 413
 414         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 415
 416         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 417                         freq);
 418         return freq;
 419 }
 420
 421 unsigned long get_board_sys_clk(ulong dummy)
 422 {
 423         u8 *pixis_base = (u8 *)PIXIS_BASE;
 424
 425         return ics307_clk_freq (
 426                         in_8(pixis_base + PIXIS_VSYSCLK0),
 427                         in_8(pixis_base + PIXIS_VSYSCLK1),
 428                         in_8(pixis_base + PIXIS_VSYSCLK2)
 429                         );
 430 }
 431
 432 unsigned long get_board_ddr_clk(ulong dummy)
 433 {
 434         u8 *pixis_base = (u8 *)PIXIS_BASE;
 435
 436         return ics307_clk_freq (
 437                         in_8(pixis_base + PIXIS_VDDRCLK0),
 438                         in_8(pixis_base + PIXIS_VDDRCLK1),
 439                         in_8(pixis_base + PIXIS_VDDRCLK2)
 440                         );
 441 }
 442 #else
 443 unsigned long get_board_sys_clk(ulong dummy)
 444 {
 445         u8 i;
 446         ulong val = 0;
 447         u8 *pixis_base = (u8 *)PIXIS_BASE;
 448
 449         i = in_8(pixis_base + PIXIS_SPD);
 450         i &= 0x07;
 451
 452         switch (i) {
 453                 case 0:
 454                         val = 33333333;
 455                         break;
 456                 case 1:
 457                         val = 40000000;
 458                         break;
 459                 case 2:
 460                         val = 50000000;
 461                         break;
 462                 case 3:
 463                         val = 66666666;
 464                         break;
 465                 case 4:
 466                         val = 83333333;
 467                         break;
 468                 case 5:
 469                         val = 100000000;
 470                         break;
 471                 case 6:
 472                         val = 133333333;
 473                         break;
 474                 case 7:
 475                         val = 166666666;
 476                         break;
 477         }
 478
 479         return val;
 480 }
 481
 482 unsigned long get_board_ddr_clk(ulong dummy)
 483 {
 484         u8 i;
 485         ulong val = 0;
 486         u8 *pixis_base = (u8 *)PIXIS_BASE;
 487
 488         i = in_8(pixis_base + PIXIS_SPD);
 489         i &= 0x38;
 490         i >>= 3;
 491
 492         switch (i) {
 493                 case 0:
 494                         val = 33333333;
 495                         break;
 496                 case 1:
 497                         val = 40000000;
 498                         break;
 499                 case 2:
 500                         val = 50000000;
 501                         break;
 502                 case 3:
 503                         val = 66666666;
 504                         break;
 505                 case 4:
 506                         val = 83333333;
 507                         break;
 508                 case 5:
 509                         val = 100000000;
 510                         break;
 511                 case 6:
 512                         val = 133333333;
 513                         break;
 514                 case 7:
 515                         val = 166666666;
 516                         break;
 517         }
 518         return val;
 519 }
 520 #endif
 521
 522 #ifdef CONFIG_TSEC_ENET
 523 int board_eth_init(bd_t *bis)
 524 {
 525         struct tsec_info_struct tsec_info[4];
 526         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 527         int num = 0;
 528
 529 #ifdef CONFIG_TSEC1
 530         SET_STD_TSEC_INFO(tsec_info[num], 1);
 531         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 532                 tsec_info[num].flags |= TSEC_SGMII;
 533         num++;
 534 #endif
 535 #ifdef CONFIG_TSEC2
 536         SET_STD_TSEC_INFO(tsec_info[num], 2);
 537         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 538                 tsec_info[num].flags |= TSEC_SGMII;
 539         num++;
 540 #endif
 541 #ifdef CONFIG_TSEC3
 542         SET_STD_TSEC_INFO(tsec_info[num], 3);
 543         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 544                 tsec_info[num].flags |= TSEC_SGMII;
 545         num++;
 546 #endif
 547 #ifdef CONFIG_TSEC4
 548         SET_STD_TSEC_INFO(tsec_info[num], 4);
 549         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 550                 tsec_info[num].flags |= TSEC_SGMII;
 551         num++;
 552 #endif
 553
 554         if (!num) {
 555                 printf("No TSECs initialized\n");
 556
 557                 return 0;
 558         }
 559
 560 #ifdef CONFIG_FSL_SGMII_RISER
 561         fsl_sgmii_riser_init(tsec_info, num);
 562 #endif
 563
 564         tsec_eth_init(bis, tsec_info, num);
 565
 566         return pci_eth_init(bis);
 567 }
 568 #endif
 569
 570 #if defined(CONFIG_OF_BOARD_SETUP)
 571 void ft_board_setup(void *blob, bd_t *bd)
 572 {
 573         phys_addr_t base;
 574         phys_size_t size;
 575
 576         ft_cpu_setup(blob, bd);
 577
 578         base = getenv_bootm_low();
 579         size = getenv_bootm_size();
 580
 581         fdt_fixup_memory(blob, (u64)base, (u64)size);
 582
 583 #ifdef CONFIG_PCIE3
 584         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 585 #endif
 586 #ifdef CONFIG_PCIE2
 587         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 588 #endif
 589 #ifdef CONFIG_PCIE1
 590         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 591 #endif
 592 #ifdef CONFIG_FSL_SGMII_RISER
 593         fsl_sgmii_riser_fdt_fixup(blob);
 594 #endif
 595 }
 596 #endif
 597
 598 #ifdef CONFIG_MP
 599 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 600
 601 void board_lmb_reserve(struct lmb *lmb)
 602 {
 603         cpu_mp_lmb_reserve(lmb);
 604 }
 605 #endif