2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
41 long int fixed_sdram(void);
45 printf ("Board: MPC8572DS, System ID: 0x%02x, "
46 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
47 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
48 in8(PIXIS_BASE + PIXIS_PVER));
52 phys_size_t initdram(int board_type)
54 phys_size_t dram_size = 0;
56 puts("Initializing....");
58 #ifdef CONFIG_SPD_EEPROM
59 dram_size = fsl_ddr_sdram();
61 dram_size = fixed_sdram();
63 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
64 dram_size *= 0x100000;
70 #if !defined(CONFIG_SPD_EEPROM)
72 * Fixed sdram init -- doesn't use serial presence detect.
75 phys_size_t fixed_sdram (void)
77 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
78 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
81 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
82 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
84 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
85 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
86 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
87 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
88 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
89 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
90 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
91 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
92 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
93 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
95 #if defined (CONFIG_DDR_ECC)
96 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
97 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
98 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
104 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
106 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
108 debug("DDR - 1st controller: memory initializing\n");
110 * Poll until memory is initialized.
111 * 512 Meg at 400 might hit this 200 times or so.
113 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
116 debug("DDR: memory initialized\n\n");
121 return 512 * 1024 * 1024;
127 static struct pci_controller pcie1_hose;
131 static struct pci_controller pcie2_hose;
135 static struct pci_controller pcie3_hose;
138 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
139 extern void fsl_pci_init(struct pci_controller *hose);
141 int first_free_busno=0;
143 void pci_init_board(void)
145 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
146 uint devdisr = gur->devdisr;
147 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
148 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
150 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
151 devdisr, io_sel, host_agent);
153 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
154 printf (" eTSEC1 is in sgmii mode.\n");
155 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
156 printf (" eTSEC2 is in sgmii mode.\n");
157 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
158 printf (" eTSEC3 is in sgmii mode.\n");
159 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
160 printf (" eTSEC4 is in sgmii mode.\n");
165 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
166 struct pci_controller *hose = &pcie3_hose;
167 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
168 (host_agent == 5) || (host_agent == 6);
169 int pcie_configured = (io_sel == 0x7);
170 struct pci_region *r = hose->regions;
173 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
174 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
175 pcie_ep ? "End Point" : "Root Complex",
177 if (pci->pme_msg_det) {
178 pci->pme_msg_det = 0xffffffff;
179 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
184 r += fsl_pci_setup_inbound_windows(r);
186 /* outbound memory */
188 CONFIG_SYS_PCIE3_MEM_BUS,
189 CONFIG_SYS_PCIE3_MEM_PHYS,
190 CONFIG_SYS_PCIE3_MEM_SIZE,
195 CONFIG_SYS_PCIE3_IO_BUS,
196 CONFIG_SYS_PCIE3_IO_PHYS,
197 CONFIG_SYS_PCIE3_IO_SIZE,
200 hose->region_count = r - hose->regions;
201 hose->first_busno=first_free_busno;
202 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
206 first_free_busno=hose->last_busno+1;
207 printf (" PCIE3 on bus %02x - %02x\n",
208 hose->first_busno,hose->last_busno);
211 * Activate ULI1575 legacy chip by performing a fake
212 * memory access. Needed to make ULI RTC work.
213 * Device 1d has the first on-board memory BAR.
216 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
217 PCI_BASE_ADDRESS_1, &temp32);
218 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
219 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
221 debug(" uli1572 read to %p\n", p);
225 printf (" PCIE3: disabled\n");
230 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
235 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
236 struct pci_controller *hose = &pcie2_hose;
237 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
238 (host_agent == 6) || (host_agent == 0);
239 int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
240 struct pci_region *r = hose->regions;
242 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
243 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
244 pcie_ep ? "End Point" : "Root Complex",
246 if (pci->pme_msg_det) {
247 pci->pme_msg_det = 0xffffffff;
248 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
253 r += fsl_pci_setup_inbound_windows(r);
255 /* outbound memory */
257 CONFIG_SYS_PCIE2_MEM_BUS,
258 CONFIG_SYS_PCIE2_MEM_PHYS,
259 CONFIG_SYS_PCIE2_MEM_SIZE,
264 CONFIG_SYS_PCIE2_IO_BUS,
265 CONFIG_SYS_PCIE2_IO_PHYS,
266 CONFIG_SYS_PCIE2_IO_SIZE,
269 hose->region_count = r - hose->regions;
270 hose->first_busno=first_free_busno;
271 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
274 first_free_busno=hose->last_busno+1;
275 printf (" PCIE2 on bus %02x - %02x\n",
276 hose->first_busno,hose->last_busno);
279 printf (" PCIE2: disabled\n");
284 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
288 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
289 struct pci_controller *hose = &pcie1_hose;
290 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
292 int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
293 (io_sel == 0x7) || (io_sel == 0xb) ||
294 (io_sel == 0xc) || (io_sel == 0xf);
295 struct pci_region *r = hose->regions;
297 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
298 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
299 pcie_ep ? "End Point" : "Root Complex",
301 if (pci->pme_msg_det) {
302 pci->pme_msg_det = 0xffffffff;
303 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
308 r += fsl_pci_setup_inbound_windows(r);
310 /* outbound memory */
312 CONFIG_SYS_PCIE1_MEM_BUS,
313 CONFIG_SYS_PCIE1_MEM_PHYS,
314 CONFIG_SYS_PCIE1_MEM_SIZE,
319 CONFIG_SYS_PCIE1_IO_BUS,
320 CONFIG_SYS_PCIE1_IO_PHYS,
321 CONFIG_SYS_PCIE1_IO_SIZE,
324 hose->region_count = r - hose->regions;
325 hose->first_busno=first_free_busno;
327 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
331 first_free_busno=hose->last_busno+1;
332 printf(" PCIE1 on bus %02x - %02x\n",
333 hose->first_busno,hose->last_busno);
336 printf (" PCIE1: disabled\n");
341 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
346 int board_early_init_r(void)
348 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
349 const u8 flash_esel = 2;
352 * Remap Boot flash + PROMJET region to caching-inhibited
353 * so that flash can be erased properly.
356 /* Flush d-cache and invalidate i-cache of any FLASH data */
360 /* invalidate existing TLB entry for flash + promjet */
361 disable_tlb(flash_esel);
363 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
364 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
365 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
370 #ifdef CONFIG_GET_CLK_FROM_ICS307
371 /* decode S[0-2] to Output Divider (OD) */
372 static unsigned char ics307_S_to_OD[] = {
373 10, 2, 8, 4, 5, 7, 3, 6
376 /* Calculate frequency being generated by ICS307-02 clock chip based upon
377 * the control bytes being programmed into it. */
378 /* XXX: This function should probably go into a common library */
380 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
382 const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
383 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
384 unsigned long RDW = cw2 & 0x7F;
385 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
388 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
390 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
391 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
392 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
394 * R6:R0 = Reference Divider Word (RDW)
395 * V8:V0 = VCO Divider Word (VDW)
396 * S2:S0 = Output Divider Select (OD)
397 * F1:F0 = Function of CLK2 Output
399 * C1:C0 = internal load capacitance for cyrstal
402 /* Adding 1 to get a "nicely" rounded number, but this needs
403 * more tweaking to get a "properly" rounded number. */
405 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
407 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
412 unsigned long get_board_sys_clk(ulong dummy)
414 return ics307_clk_freq (
415 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
416 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
417 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
421 unsigned long get_board_ddr_clk(ulong dummy)
423 return ics307_clk_freq (
424 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
425 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
426 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
430 unsigned long get_board_sys_clk(ulong dummy)
435 i = in8(PIXIS_BASE + PIXIS_SPD);
468 unsigned long get_board_ddr_clk(ulong dummy)
473 i = in8(PIXIS_BASE + PIXIS_SPD);
507 #ifdef CONFIG_TSEC_ENET
508 int board_eth_init(bd_t *bis)
510 struct tsec_info_struct tsec_info[4];
511 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
515 SET_STD_TSEC_INFO(tsec_info[num], 1);
516 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
517 tsec_info[num].flags |= TSEC_SGMII;
521 SET_STD_TSEC_INFO(tsec_info[num], 2);
522 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
523 tsec_info[num].flags |= TSEC_SGMII;
527 SET_STD_TSEC_INFO(tsec_info[num], 3);
528 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
529 tsec_info[num].flags |= TSEC_SGMII;
533 SET_STD_TSEC_INFO(tsec_info[num], 4);
534 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
535 tsec_info[num].flags |= TSEC_SGMII;
540 printf("No TSECs initialized\n");
545 fsl_sgmii_riser_init(tsec_info, num);
547 tsec_eth_init(bis, tsec_info, num);
553 #if defined(CONFIG_OF_BOARD_SETUP)
554 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
555 struct pci_controller *hose);
557 void ft_board_setup(void *blob, bd_t *bd)
561 ft_cpu_setup(blob, bd);
563 base = getenv_bootm_low();
564 size = getenv_bootm_size();
566 fdt_fixup_memory(blob, (u64)base, (u64)size);
569 ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
572 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
575 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
581 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
583 void board_lmb_reserve(struct lmb *lmb)
585 cpu_mp_lmb_reserve(lmb);