2 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_86xx.h>
28 #include <asm/fsl_pci.h>
29 #include <asm/fsl_ddr_sdram.h>
33 #include <fdt_support.h>
34 #include <spd_sdram.h>
37 void sdram_init(void);
38 phys_size_t fixed_sdram(void);
39 int mpc8610hpcd_diu_init(void);
42 /* called before any console output */
43 int board_early_init_f(void)
45 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
46 volatile ccsr_gur_t *gur = &immap->im_gur;
48 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
56 u8 *pixis_base = (u8 *)PIXIS_BASE;
58 /*Do not use 8259PIC*/
59 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
60 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
62 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
63 version = in_8(pixis_base + PIXIS_PVER);
65 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
66 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
69 /* Using this for DIU init before the driver in linux takes over
70 * Enable the TFP410 Encoder (I2C address 0x38)
74 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
75 /* Verify if enabled */
77 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
78 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
81 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
82 /* Verify if enabled */
84 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
85 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
92 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
93 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
94 u8 *pixis_base = (u8 *)PIXIS_BASE;
96 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
97 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
98 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
99 in_8(pixis_base + PIXIS_PVER));
101 mcm->abcr |= 0x00010000; /* 0 */
102 mcm->hpmr3 = 0x80000008; /* 4c */
114 initdram(int board_type)
116 phys_size_t dram_size = 0;
118 #if defined(CONFIG_SPD_EEPROM)
119 dram_size = fsl_ddr_sdram();
121 dram_size = fixed_sdram();
124 setup_ddr_bat(dram_size);
131 #if !defined(CONFIG_SPD_EEPROM)
133 * Fixed sdram init -- doesn't use serial presence detect.
136 phys_size_t fixed_sdram(void)
138 #if !defined(CONFIG_SYS_RAMBOOT)
139 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
140 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
143 ddr->cs0_bnds = 0x0000001f;
144 ddr->cs0_config = 0x80010202;
146 ddr->timing_cfg_3 = 0x00000000;
147 ddr->timing_cfg_0 = 0x00260802;
148 ddr->timing_cfg_1 = 0x3935d322;
149 ddr->timing_cfg_2 = 0x14904cc8;
150 ddr->sdram_mode = 0x00480432;
151 ddr->sdram_mode_2 = 0x00000000;
152 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
153 ddr->sdram_data_init = 0xDEADBEEF;
154 ddr->sdram_clk_cntl = 0x03800000;
155 ddr->sdram_cfg_2 = 0x04400010;
157 #if defined(CONFIG_DDR_ECC)
158 ddr->err_int_en = 0x0000000d;
159 ddr->err_disable = 0x00000000;
160 ddr->err_sbe = 0x00010000;
166 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
169 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
171 debug("DDR - 1st controller: memory initializing\n");
173 * Poll until memory is initialized.
174 * 512 Meg at 400 might hit this 200 times or so.
176 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
179 debug("DDR: memory initialized\n\n");
184 return 512 * 1024 * 1024;
186 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
191 #if defined(CONFIG_PCI)
193 * Initialize PCI Devices, report devices found.
196 #ifndef CONFIG_PCI_PNP
197 static struct pci_config_table pci_fsl86xxads_config_table[] = {
198 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
199 PCI_IDSEL_NUMBER, PCI_ANY_ID,
200 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
202 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
208 static struct pci_controller pci1_hose = {
209 #ifndef CONFIG_PCI_PNP
210 config_table:pci_mpc86xxcts_config_table
213 #endif /* CONFIG_PCI */
216 static struct pci_controller pcie1_hose;
220 static struct pci_controller pcie2_hose;
223 void pci_init_board(void)
225 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
226 volatile ccsr_gur_t *gur = &immap->im_gur;
227 struct fsl_pci_info pci_info[3];
228 u32 devdisr, pordevsr, io_sel;
229 int first_free_busno = 0;
232 int pci_agent, pcie_ep, pcie_configured;
234 devdisr = in_be32(&gur->devdisr);
235 pordevsr = in_be32(&gur->pordevsr);
236 io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL)
237 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
239 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
242 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
244 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
245 SET_STD_PCIE_INFO(pci_info[num], 1);
246 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
247 printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
248 pcie_ep ? "Endpoint" : "Root Complex",
251 first_free_busno = fsl_pci_init_port(&pci_info[num++],
252 &pcie1_hose, first_free_busno);
254 printf (" PCIE1: disabled\n");
259 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */
263 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
265 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
266 SET_STD_PCIE_INFO(pci_info[num], 2);
267 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
268 printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
269 pcie_ep ? "Endpoint" : "Root Complex",
271 first_free_busno = fsl_pci_init_port(&pci_info[num++],
272 &pcie2_hose, first_free_busno);
274 printf (" PCIE2: disabled\n");
279 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */
283 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
284 SET_STD_PCI_INFO(pci_info[num], 1);
285 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
286 printf(" PCI connected to PCI slots as %s" \
287 " (base address %lx)\n",
288 pci_agent ? "Agent" : "Host",
290 first_free_busno = fsl_pci_init_port(&pci_info[num++],
291 &pci1_hose, first_free_busno);
293 printf (" PCI: disabled\n");
298 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
302 #if defined(CONFIG_OF_BOARD_SETUP)
304 ft_board_setup(void *blob, bd_t *bd)
306 ft_cpu_setup(blob, bd);
314 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
318 get_board_sys_clk(ulong dummy)
322 u8 *pixis_base = (u8 *)PIXIS_BASE;
324 i = in_8(pixis_base + PIXIS_SPD);
357 int board_eth_init(bd_t *bis)
359 return pci_eth_init(bis);
362 void board_reset(void)
364 u8 *pixis_base = (u8 *)PIXIS_BASE;
366 out_8(pixis_base + PIXIS_RST, 0);