2 * Copyright 2006, 2007, 2010 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 phys_size_t fixed_sdram(void);
36 int board_early_init_f(void)
44 u8 *pixis_base = (u8 *)PIXIS_BASE;
46 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
47 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
48 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
49 in_8(pixis_base + PIXIS_PVER));
51 vboot = in_8(pixis_base + PIXIS_VBOOT);
52 if (vboot & PIXIS_VBOOT_FMAP)
53 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
57 #ifdef CONFIG_PHYS_64BIT
58 printf (" 36-bit physical address map\n");
63 const char *board_hwconfig = "foo:bar=baz";
64 const char *cpu_hwconfig = "foo:bar=baz";
67 initdram(int board_type)
69 phys_size_t dram_size = 0;
71 #if defined(CONFIG_SPD_EEPROM)
72 dram_size = fsl_ddr_sdram();
74 dram_size = fixed_sdram();
77 setup_ddr_bat(dram_size);
84 #if !defined(CONFIG_SPD_EEPROM)
86 * Fixed sdram init -- doesn't use serial presence detect.
91 #if !defined(CONFIG_SYS_RAMBOOT)
92 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
93 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
95 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
96 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
97 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
98 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
99 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
100 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
101 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
102 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
103 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
104 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
105 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
106 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
107 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
109 #if defined (CONFIG_DDR_ECC)
110 ddr->err_disable = 0x0000008D;
111 ddr->err_sbe = 0x00ff0000;
117 #if defined (CONFIG_DDR_ECC)
118 /* Enable ECC checking */
119 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
121 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
122 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
128 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
130 #endif /* !defined(CONFIG_SPD_EEPROM) */
133 #if defined(CONFIG_PCI)
134 static struct pci_controller pcie1_hose;
135 #endif /* CONFIG_PCI */
138 static struct pci_controller pcie2_hose;
139 #endif /* CONFIG_PCIE2 */
141 int first_free_busno = 0;
143 void pci_init_board(void)
145 struct fsl_pci_info pci_info[2];
150 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
151 volatile ccsr_gur_t *gur = &immap->im_gur;
152 uint devdisr = in_be32(&gur->devdisr);
153 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
154 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
155 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
157 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
158 SET_STD_PCIE_INFO(pci_info[num], 1);
159 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
160 printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
161 pcie_ep ? "Endpoint" : "Root Complex",
163 first_free_busno = fsl_pci_init_port(&pci_info[num++],
164 &pcie1_hose, first_free_busno);
167 * Activate ULI1575 legacy chip by performing a fake
168 * memory access. Needed to make ULI RTC work.
170 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
171 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
174 puts("PCIE1: disabled\n");
177 puts("PCIE1: disabled\n");
178 #endif /* CONFIG_PCIE1 */
181 SET_STD_PCIE_INFO(pci_info[num], 2);
182 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
183 printf("PCIE2: connected as %s (base addr %lx)\n",
184 pcie_ep ? "Endpoint" : "Root Complex",
186 first_free_busno = fsl_pci_init_port(&pci_info[num++],
187 &pcie2_hose, first_free_busno);
189 puts("PCIE2: disabled\n");
190 #endif /* CONFIG_PCIE2 */
195 #if defined(CONFIG_OF_BOARD_SETUP)
197 ft_board_setup(void *blob, bd_t *bd)
203 ft_cpu_setup(blob, bd);
208 * Warn if it looks like the device tree doesn't match u-boot.
209 * This is just an estimation, based on the location of CCSR,
210 * which is defined by the "reg" property in the soc node.
212 off = fdt_path_offset(blob, "/soc8641");
213 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
214 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
218 if (addrcells && (*addrcells == 1))
223 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
224 printf("WARNING: The CCSRBAR address in your .dts "
225 "does not match the address of the CCSR "
226 "in u-boot. This means your .dts might "
235 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
239 get_board_sys_clk(ulong dummy)
241 u8 i, go_bit, rd_clks;
243 u8 *pixis_base = (u8 *)PIXIS_BASE;
245 go_bit = in_8(pixis_base + PIXIS_VCTL);
248 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
252 * Only if both go bit and the SCLK bit in VCFGEN0 are set
253 * should we be using the AUX register. Remember, we also set the
254 * GO bit to boot from the alternate bank on the on-board flash
259 i = in_8(pixis_base + PIXIS_AUX);
261 i = in_8(pixis_base + PIXIS_SPD);
263 i = in_8(pixis_base + PIXIS_SPD);
298 int board_eth_init(bd_t *bis)
300 /* Initialize TSECs */
302 return pci_eth_init(bis);
305 void board_reset(void)
307 u8 *pixis_base = (u8 *)PIXIS_BASE;
309 out_8(pixis_base + PIXIS_RST, 0);
316 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
318 void board_lmb_reserve(struct lmb *lmb)
320 cpu_mp_lmb_reserve(lmb);