2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/fsl_pci.h>
28 #include <asm/fsl_ddr_sdram.h>
31 #include <fdt_support.h>
34 phys_size_t fixed_sdram(void);
36 int board_early_init_f(void)
44 u8 *pixis_base = (u8 *)PIXIS_BASE;
46 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
47 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
48 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
49 in_8(pixis_base + PIXIS_PVER));
51 vboot = in_8(pixis_base + PIXIS_VBOOT);
52 if (vboot & PIXIS_VBOOT_FMAP)
53 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
57 #ifdef CONFIG_PHYS_64BIT
58 printf (" 36-bit physical address map\n");
65 initdram(int board_type)
67 phys_size_t dram_size = 0;
69 #if defined(CONFIG_SPD_EEPROM)
70 dram_size = fsl_ddr_sdram();
72 dram_size = fixed_sdram();
75 setup_ddr_bat(dram_size);
82 #if !defined(CONFIG_SPD_EEPROM)
84 * Fixed sdram init -- doesn't use serial presence detect.
89 #if !defined(CONFIG_SYS_RAMBOOT)
90 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
91 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
93 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
94 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
95 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
96 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
97 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
98 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
99 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
100 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
101 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
102 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
103 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
104 ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
105 ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
107 #if defined (CONFIG_DDR_ECC)
108 ddr->err_disable = 0x0000008D;
109 ddr->err_sbe = 0x00ff0000;
115 #if defined (CONFIG_DDR_ECC)
116 /* Enable ECC checking */
117 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
119 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
120 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
126 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
128 #endif /* !defined(CONFIG_SPD_EEPROM) */
131 #if defined(CONFIG_PCI)
132 static struct pci_controller pci1_hose;
133 #endif /* CONFIG_PCI */
136 static struct pci_controller pci2_hose;
137 #endif /* CONFIG_PCI2 */
139 int first_free_busno = 0;
141 void pci_init_board(void)
145 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
146 struct pci_controller *hose = &pci1_hose;
147 struct pci_region *r = hose->regions;
148 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
149 volatile ccsr_gur_t *gur = &immap->im_gur;
150 uint devdisr = gur->devdisr;
151 uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
152 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
153 int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
156 uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
157 >> MPC8641_PORBMSR_HA_SHIFT;
158 uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
160 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
161 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
162 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
163 if (pci->pme_msg_det) {
164 pci->pme_msg_det = 0xffffffff;
165 debug(" with errors. Clearing. Now 0x%08x",
170 /* outbound memory */
172 CONFIG_SYS_PCI1_MEM_BUS,
173 CONFIG_SYS_PCI1_MEM_PHYS,
174 CONFIG_SYS_PCI1_MEM_SIZE,
179 CONFIG_SYS_PCI1_IO_BUS,
180 CONFIG_SYS_PCI1_IO_PHYS,
181 CONFIG_SYS_PCI1_IO_SIZE,
184 hose->region_count = r - hose->regions;
186 hose->first_busno=first_free_busno;
188 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
190 first_free_busno=hose->last_busno+1;
191 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
192 hose->first_busno,hose->last_busno);
195 * Activate ULI1575 legacy chip by performing a fake
196 * memory access. Needed to make ULI RTC work.
198 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
199 + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
202 puts("PCI-EXPRESS 1: Disabled\n");
206 puts("PCI-EXPRESS1: Disabled\n");
207 #endif /* CONFIG_PCI1 */
211 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
212 struct pci_controller *hose = &pci2_hose;
213 struct pci_region *r = hose->regions;
215 /* outbound memory */
217 CONFIG_SYS_PCI2_MEM_BUS,
218 CONFIG_SYS_PCI2_MEM_PHYS,
219 CONFIG_SYS_PCI2_MEM_SIZE,
224 CONFIG_SYS_PCI2_IO_BUS,
225 CONFIG_SYS_PCI2_IO_PHYS,
226 CONFIG_SYS_PCI2_IO_SIZE,
229 hose->region_count = r - hose->regions;
231 hose->first_busno=first_free_busno;
233 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
235 first_free_busno=hose->last_busno+1;
236 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
237 hose->first_busno,hose->last_busno);
240 puts("PCI-EXPRESS 2: Disabled\n");
241 #endif /* CONFIG_PCI2 */
246 #if defined(CONFIG_OF_BOARD_SETUP)
248 ft_board_setup(void *blob, bd_t *bd)
254 ft_cpu_setup(blob, bd);
257 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
260 ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
264 * Warn if it looks like the device tree doesn't match u-boot.
265 * This is just an estimation, based on the location of CCSR,
266 * which is defined by the "reg" property in the soc node.
268 off = fdt_path_offset(blob, "/soc8641");
269 addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
270 tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
274 if (addrcells && (*addrcells == 1))
279 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
280 printf("WARNING: The CCSRBAR address in your .dts "
281 "does not match the address of the CCSR "
282 "in u-boot. This means your .dts might "
291 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
295 get_board_sys_clk(ulong dummy)
297 u8 i, go_bit, rd_clks;
299 u8 *pixis_base = (u8 *)PIXIS_BASE;
301 go_bit = in_8(pixis_base + PIXIS_VCTL);
304 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
308 * Only if both go bit and the SCLK bit in VCFGEN0 are set
309 * should we be using the AUX register. Remember, we also set the
310 * GO bit to boot from the alternate bank on the on-board flash
315 i = in_8(pixis_base + PIXIS_AUX);
317 i = in_8(pixis_base + PIXIS_SPD);
319 i = in_8(pixis_base + PIXIS_SPD);
354 int board_eth_init(bd_t *bis)
356 /* Initialize TSECs */
358 return pci_eth_init(bis);
361 void board_reset(void)
363 u8 *pixis_base = (u8 *)PIXIS_BASE;
365 out_8(pixis_base + PIXIS_RST, 0);
372 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
374 void board_lmb_reserve(struct lmb *lmb)
376 cpu_mp_lmb_reserve(lmb);