12 menu "mx6memcal specifics"
14 prompt "Serial console"
16 Either UART1 or UART2 will be used as the console for
17 displaying the calibration values or errors.
19 config SERIAL_CONSOLE_UART1
22 Select this if your board uses UART1 for its' console.
24 config SERIAL_CONSOLE_UART2
27 Select this if your board uses UART2 for its' console.
34 Select the RX and TX pads used for your serial console.
35 The choices below reflect the most commonly used options
38 config UART2_EIM_D26_27
39 bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
40 depends on SERIAL_CONSOLE_UART2
42 Choose this configuration if you're using pads
43 EIM_D26 and D27 for a console on UART2.
44 This is typical for designs that are based on the
47 config UART1_CSI0_DAT10_11
48 bool "UART1 on CSI0_DAT10/11 (Wand)"
49 depends on SERIAL_CONSOLE_UART1
51 Choose this configuration if you're using pads
52 CSI0_DAT10 and DAT11 for a console on UART1 as
53 is done on the i.MX6 Wand board.
55 config UART1_SD3_DAT6_7
56 bool "UART1 on SD3_DAT6/7 (SabreSD, SabreAuto)"
57 depends on SERIAL_CONSOLE_UART1
59 Choose this configuration if you're using pads
60 SD3_DAT6 and DAT7 for a console on UART1 as is
61 done on the NXP SABRESD or SABREAUTO designs.
64 bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
65 depends on SERIAL_CONSOLE_UART1
67 Choose this configuration if you're using pads
68 UART1_TXD/RXD for a console on UART1 as is done
69 on most i.MX6SL designs.
73 config IMXIMAGE_OUTPUT
74 bool "Include output for imximage .cfg files"
77 Say "Y" if you want output formatted for use in non-SPL
78 (DCD-style) configuration files.
84 Select either 32 or 64 to reflect the DDR bus width.
87 int "DDR chip selects"
91 Select the number of chip selects used in your board design
96 Select the type of DDR (DDR3 or LPDDR2) used on your design
101 Select this if your board design uses DDR3.
106 Select this if your board design uses LPDDR2.
111 prompt "Memory device"
113 config MT41K512M16TNA
114 bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
118 bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
122 bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
126 bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
129 config MT42L256M32D2LG
130 bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
133 config MT29PZZZ4D4BKESK
134 bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
140 int "DDR On-die-termination"
144 Enter the on-die termination value as an index defined for
145 IOMUX settings for PAD_DRAM_SDCLK0_P and others.
154 Value will be applied to all clock and data lines
157 config DRAM_DRIVE_STRENGTH
158 int "DRAM Drive strength"
162 Enter drive strength as an index defined for IOMUX settings
163 for GRP_B1DS and others.
165 6 == 40 Ohm (default)
167 Value will be applied to all clock and data lines
174 Enter the RTT_NOM selector
183 Enter the RTT_WR selector for MR2
184 0 == Dynamic ODT disabled
189 int "Read additional latency"
193 Enter a latency in number of cycles. This will be added to
194 CAS and internal delays for which the MMDC will retrieve the
195 read data from the internal FIFO.
196 This is used to compensate for board/chip delays.
199 int "Write additional latency"
203 Enter a latency in number of cycles. This will be added to
204 CAS and internal delays for which the MMDC will retrieve the
205 read data from the internal FIFO
206 This is used to compensate for board/chip delays.
213 Select the DDR refresh period.
214 See the description of bitfield REF_SEL in the reference manual
222 int "Number of refreshes"
226 This selects the number of refreshes (-1) during each period.
228 0 == 1 refresh (tRFC)
229 7 == 8 refreshes (tRFC*8)
230 See the description of MDREF[REFR] in the reference manual for