2 * Copyright 2010 Freescale Semiconductor, Inc.
3 * Authors: Timur Tabi <timur@freescale.com>
5 * FSL DIU Framebuffer driver
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
16 #include <stdio_dev.h>
18 #include "../common/ngpixis.h"
19 #include <fsl_diu_fb.h>
21 /* The CTL register is called 'csr' in the ngpixis_t structure */
22 #define PX_CTL_ALTACC 0x80
24 #define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
25 #define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
26 #define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
27 #define PX_BRDCFG0_ELBC_DIU 0x02
29 #define PX_BRDCFG1_DVIEN 0x80
30 #define PX_BRDCFG1_DFPEN 0x40
31 #define PX_BRDCFG1_BACKLIGHT 0x20
33 #define PMUXCR_ELBCDIU_MASK 0xc0000000
34 #define PMUXCR_ELBCDIU_NOR16 0x80000000
39 * Note that we need to byte-swap the value before it's written to the AD
40 * register. So even though the registers don't look like they're in the same
41 * bit positions as they are on the MPC8610, the same value is written to the
42 * AD register on the MPC8610 and on the P1022.
44 #define AD_BYTE_F 0x10000000
45 #define AD_ALPHA_C_SHIFT 25
46 #define AD_BLUE_C_SHIFT 23
47 #define AD_GREEN_C_SHIFT 21
48 #define AD_RED_C_SHIFT 19
49 #define AD_PIXEL_S_SHIFT 16
50 #define AD_COMP_3_SHIFT 12
51 #define AD_COMP_2_SHIFT 8
52 #define AD_COMP_1_SHIFT 4
53 #define AD_COMP_0_SHIFT 0
56 * Variables used by the DIU/LBC switching code. It's safe to makes these
57 * global, because the DIU requires DDR, so we'll only run this code after
62 static void *lbc_lcs0_ba;
63 static void *lbc_lcs1_ba;
65 void diu_set_pixel_clock(unsigned int pixclock)
67 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68 unsigned long speed_ccb, temp;
71 speed_ccb = get_bus_freq(0);
72 temp = 1000000000 / pixclock;
74 pixval = speed_ccb / temp;
75 debug("DIU pixval = %lu\n", pixval);
77 /* Modify PXCLK in GUTS CLKDVDR */
78 temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
79 out_be32(&gur->clkdvdr, temp); /* turn off clock */
80 out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
83 int platform_diu_init(unsigned int *xres, unsigned int *yres)
85 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
90 /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
91 lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000);
92 lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000);
94 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
95 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
96 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
97 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
98 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
100 temp = in_8(&pixis->brdcfg1);
102 monitor_port = getenv("monitor");
103 if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
106 /* Enable the DFP port, disable the DVI and the backlight */
107 temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT);
108 temp |= PX_BRDCFG1_DFPEN;
112 /* Enable the DVI port, disable the DFP and the backlight */
113 temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
114 temp |= PX_BRDCFG1_DVIEN;
117 out_8(&pixis->brdcfg1, temp);
120 * Enable PIXIS indirect access mode. This is a hack that allows us to
121 * access PIXIS registers even when the LBC pins have been muxed to the
124 setbits_8(&pixis->csr, PX_CTL_ALTACC);
127 * Route the LAD pins to the DIU. This will disable access to the eLBC,
128 * which means we won't be able to read/write any NOR flash addresses!
130 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
131 px_brdcfg0 = in_8(lbc_lcs1_ba);
132 out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
134 /* Setting PMUXCR to switch to DVI from ELBC */
135 clrsetbits_be32(&gur->pmuxcr,
136 PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16);
137 pmuxcr = in_be32(&gur->pmuxcr);
139 return fsl_diu_init(*xres, pixel_format, 0);
142 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
145 * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
147 * On the Freescale P1022, the DIU video signal and the LBC address/data lines
148 * share the same pins, which means that when the DIU is active (e.g. the
149 * console is on the DVI display), NOR flash cannot be accessed. So we use the
150 * weak accessor feature of the CFI flash code to temporarily switch the pin
151 * mux from DIU to LBC whenever we want to read or write flash. This has a
152 * significant performance penalty, but it's the only way to make it work.
154 * There are two muxes: one on the chip, and one on the board. The chip mux
155 * controls whether the pins are used for the DIU or the LBC, and it is
156 * set via PMUXCR. The board mux controls whether those signals go to
157 * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
159 static int set_mux_to_lbc(void)
161 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
163 /* Switch the muxes only if they're currently set to DIU mode */
164 if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) ==
165 PMUXCR_ELBCDIU_NOR16) {
167 * In DIU mode, the PIXIS can only be accessed indirectly
168 * since we can't read/write the LBC directly.
171 /* Set the board mux to LBC. This will disable the display. */
172 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
173 px_brdcfg0 = in_8(lbc_lcs1_ba);
174 out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK
175 | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC);
177 /* Disable indirect PIXIS mode */
178 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
179 clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
181 /* Set the chip mux to LBC mode, so that writes go to flash. */
182 out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
183 PMUXCR_ELBCDIU_NOR16);
184 in_be32(&gur->pmuxcr);
193 * set_mux_to_diu - re-enable the DIU muxing
195 * This function restores the chip and board muxing to point to the DIU.
197 static void set_mux_to_diu(void)
199 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
201 /* Enable indirect PIXIS mode */
202 setbits_8(&pixis->csr, PX_CTL_ALTACC);
204 /* Set the board mux to DIU. This will enable the display. */
205 out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
206 out_8(lbc_lcs1_ba, px_brdcfg0);
209 /* Set the chip mux to DIU mode. */
210 out_be32(&gur->pmuxcr, pmuxcr);
211 in_be32(&gur->pmuxcr);
214 void flash_write8(u8 value, void *addr)
216 int sw = set_mux_to_lbc();
218 __raw_writeb(value, addr);
223 void flash_write16(u16 value, void *addr)
225 int sw = set_mux_to_lbc();
227 __raw_writew(value, addr);
232 void flash_write32(u32 value, void *addr)
234 int sw = set_mux_to_lbc();
236 __raw_writel(value, addr);
241 void flash_write64(u64 value, void *addr)
243 int sw = set_mux_to_lbc();
245 /* There is no __raw_writeq(), so do the write manually */
246 *(volatile u64 *)addr = value;
251 u8 flash_read8(void *addr)
255 int sw = set_mux_to_lbc();
257 ret = __raw_readb(addr);
264 u16 flash_read16(void *addr)
268 int sw = set_mux_to_lbc();
270 ret = __raw_readw(addr);
277 u32 flash_read32(void *addr)
281 int sw = set_mux_to_lbc();
283 ret = __raw_readl(addr);
290 u64 flash_read64(void *addr)
294 int sw = set_mux_to_lbc();
296 /* There is no __raw_readq(), so do the read manually */
297 ret = *(volatile u64 *)addr;