2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * Authors: Roy Zang <tie-fei.zang@freescale.com>
5 * Chunhe Lan <b25806@freescale.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/cache.h>
31 #include <asm/processor.h>
33 #include <asm/immap_85xx.h>
34 #include <asm/fsl_pci.h>
35 #include <asm/fsl_ddr_sdram.h>
36 #include <asm/fsl_portals.h>
38 #include <fdt_support.h>
44 DECLARE_GLOBAL_DATA_PTR;
46 int board_early_init_f(void)
48 fsl_lbc_t *lbc = LBC_BASE_ADDR;
50 /* Set ABSWP to implement conversion of addresses in the LBC */
51 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
58 u8 *bcsr = (u8 *)BCSR_ACCESS_REG_ADDR;
60 printf("Board: P1023 RDS\n");
62 clrbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG_CLR);
63 setbits_8(&bcsr[15], BCSR15_I2C_BUS0_SEG0);
68 /* Fixed sdram init -- doesn't use serial presence detect. */
69 phys_size_t fixed_sdram(void)
71 #ifndef CONFIG_SYS_RAMBOOT
72 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
74 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
76 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
77 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
78 out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
79 out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
80 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
81 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
82 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
83 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
84 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL2);
85 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
86 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
87 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
88 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
89 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
90 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
91 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
92 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
93 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
94 out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
95 out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
96 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
98 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024ul;
102 void pci_init_board(void)
104 fsl_pcie_init_board(0);
108 int board_early_init_r(void)
110 const unsigned int flashbase = CONFIG_SYS_BCSR_BASE;
111 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
114 * Remap Boot flash + BCSR region to caching-inhibited
115 * so that flash can be erased properly.
118 /* Flush d-cache and invalidate i-cache of any FLASH data */
122 /* invalidate existing TLB entry for flash + bcsr */
123 disable_tlb(flash_esel);
125 set_tlb(1, flashbase, CONFIG_SYS_BCSR_BASE_PHYS,
126 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
127 0, flash_esel, BOOKE_PAGESZ_256M, 1);
134 unsigned long get_board_sys_clk(ulong dummy)
139 unsigned long get_board_ddr_clk(ulong dummy)
144 int board_eth_init(bd_t *bis)
146 return pci_eth_init(bis);
149 #if defined(CONFIG_OF_BOARD_SETUP)
150 void ft_board_setup(void *blob, bd_t *bd)
155 ft_cpu_setup(blob, bd);
157 base = getenv_bootm_low();
158 size = getenv_bootm_size();
160 fdt_fixup_memory(blob, (u64)base, (u64)size);